SAB 82525
SAB 82526
SAF 82525
SAF 82526
Summary
The features of the different clock modes are summarized in table 6.
Table 6
Clock Modes of HSCX
Channel Configuration
Clock Sources
DPLL REC
Control Sources
Timer
Source
Clock Mode
CCR1
CCR2
Output
via
TxCLK
TSS TIO
BRG
TRM
CD
R-Strobe
X-Strobe F-Sync
TCP
CM2, CM1, CM0
0
1
2
2
3
4
4
5
6
6
6
7
7
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
–
–
–
–
RxCLK TxCLK
RxCLK RxCLK
AxCLK
–
AxCLK
–
–
–
–
–
–
–
–
–
–
–
–
TxCLK
RxCLK
TxCLK
DPLL
DPLL
OSC
AxCLK
–
–
–
–
–
TxCLK
–
–
–
–
–
RxCLK BRG
RxCLK BRG
RxCLK BRG
–
–
DPLL
DPLL
DPLL
OSC
OSC
TxCLK
BRG/16 AxCLK
DPLL
OSC
OSC
BRG/16
DPLL
–
AxCLK
TxCLK
…
TxCLK
–
–
–
–
BRG
BRG
BRG
BRG
BRG
OSC
OSC
–
RxCLK RxCLK
(TSAR)
(TSAX)
AxCLK
TS-Control RxCLK
–
–
BRG/16
–
DPLL
OSC
OSC
OSC
OSC
OSC
DPLL
DPLL
DPLL
DPLL
DPLL
TxCLK
BRG/16 TxCLK
BRG/16
DPLL
DPLL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
TxCLK
BRG/16
BRG/16
DPLL
–
TxCLK
–
DPLL
Note: 1) The maximum data rate in an externally clocked operating mode is 4.1 Mbit/s. In an
internally clocked operating mode with an external reference clock, or using the OSC,
the maximum clock rate is 12 MHz or 19.2 MHz if the scaling factor of the BRG is
programmed to 1. The maximum data rate will be 1200 kbit/s.
2) The ratio between the receive frequency (fr) and the transmit frequency (fx) for a
channel must satisfy the condition fr/fx less than 3 in clock modes 0, 2, 6; there are no
restrictions on the phase shift. Slower transmit data rates can be realized with receive
and transmit strobes (clock mode 1).
3) The clock modes 4, 6, 7 use the internal OSC and need an external quartz crystal to
be connected at the RxCLK A-AxCLK A pins.
It is not necessary to use two separate crystals for the two serial channels, instead it is
sufficient to apply the crystal to channel A and provide the reference clock for channel
B by externally connecting the AxCLKA and RxCLKB pins. The SAB 82526 also uses
the RxCLK A-AxCLK A pins to connect to an external quartz crystal.
Semiconductor Group
56