General Information
Table of Contents
Page
1
Features..................................................................................................................... 6
Pin Definitions and Functions ................................................................................... 10
System Integration.................................................................................................... 17
Functional Description ..............................................................................................22
1.1
1.2
1.3
2
Operating Modes .....................................................................................................24
Auto-Mode (MODE: MDS1, MDS0 = 00) ..................................................................24
Non-Auto Mode (MODE: MDS1, MDS0 = 01) ..........................................................24
Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101) .......................................25
Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100) .......................................25
Extended Transparent Modes 0; 1 (MODE: MDS1, MDS0 = 11) .............................25
Receive Data Flow (Summary) .................................................................................26
Transmit Data Flow ...................................................................................................27
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
Procedural Support (Layer-2 Functions) ..............................................................28
Full-Duplex LAPB/LAPD Operation ..........................................................................28
Half-Duplex SDLC-NRM Operation ..........................................................................34
Error Handling ...........................................................................................................38
3.1
3.2
3.3
4
CPU Interface ..........................................................................................................38
Register Set .............................................................................................................. 38
Data Transfer Modes .................................................................................................38
Interrupt Interface ......................................................................................................39
DMA Interface........................................................................................................... 43
FIFO Structure ..........................................................................................................47
4.1
4.2
4.3
4.4
4.5
5
Serial Interface (Layer-1 Functions) ......................................................................49
Clock Modes ..............................................................................................................49
Clock Recovery (DPLL) ............................................................................................ 57
Bus Configuration ..................................................................................................... 60
Data Encoding ..........................................................................................................63
Modem Control Functions (RTS/CTS, CD) ...............................................................63
5.1
5.2
5.3
5.4
5.5
6
Special Functions ...................................................................................................65
Fully Transparent Transmission and Reception .......................................................65
Cyclic Transmission (Fully Transparent) ...................................................................65
Continuous Transmission (DMA Mode only) ............................................................66
Receive Length Check Feature ................................................................................66
One Bit Insertion .......................................................................................................67
Data Inversion........................................................................................................... 67
6.1
6.2
6.3
6.4
6.5
6.6
Semiconductor Group
3