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SAB82525H-V21 参数 Datasheet PDF下载

SAB82525H-V21图片预览
型号: SAB82525H-V21
PDF下载: 下载PDF文件 查看货源
内容描述: 高层次的串行通信控制器扩展 [High-Level Serial Communication Controller Extended]
分类和应用: 通信控制器
文件页数/大小: 126 页 / 741 K
品牌: SIEMENS [ Siemens Semiconductor Group ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
2
Operating Modes  
The HDLC controller of each channel can be programmed to operate in various modes, which  
are different in the treatment of the HDLC frame in receive direction. Thus, the receive data  
flow and the address recognition features can be effected in a very flexible way, which satisfies  
most requirements.  
There are 6 different operating modes which can be set via the MODE register.  
2.1 Auto-Mode (MODE: MDS1, MDS0 = 00)  
Characteristics: Window size 1, arbitrary message length, address recognition.  
The HSCX processes autonomously all numbered frames (S-, I-frames) of an HDLC  
procedure.  
The HDLC control field, data in the I-field of the frames and an additional status byte is  
temporarily stored in the RFIFO. The HDLC control field as well as additional information can  
also be read from special registers (RHCR, RSTA).  
According to the selected address mode, the HSCX can perform a 2-byte or 1-byte address  
recognition. If a 2-byte address field is selected, the high address byte is compared with the  
fixed value FE or FC (group address) as well as with two individually programmable values  
H
H
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte  
address will be interpreted as COMMAND/RESPONSE bit (C/R), dependent on the setting of  
the CRI bit in RAH1, and will be excluded from the address comparison.  
Similary, two compare values can be programmed in special registers (RAL1, RAL2) for the  
low address byte. A valid address will be recognized in case the high and low byte of the  
address field correspond to one of the compare values. Thus, the HSCX can be called  
(addressed) with 6 different address combinations, however, only the logical connection  
identified through the address combination RAH1, RAL1 will be processed in the auto-mode,  
all others in the non-auto mode. HDLC frames with address fields that do not match with any  
of the address combinations, are ignored by the HSCX.  
In case of a 1-byte address, RAL1 and RAL2 will be used as compare registers. According to  
the X.25 LAPB protocol, the value in RAL1 will be interpreted as COMMAND and the value in  
RAL2 as RESPONSE.  
After receiving a frame it takes 5 clock cycles to generate the response frame and to start  
transmission.  
2.2 Non-Auto Mode (MODE: MDS1, MDS0 = 01)  
Characteristics: address recognition, arbitrary window size.  
All frames with valid addresses (address recognition identical to auto-mode) are forwarded  
directly to the system memory.  
The HDLC control field, data in the I-field and an additional status byte are temporarily stored  
in the RFIFO. The HDLC control field and additional information can also be read from special  
registers (RHCR, RSTA).  
In non-auto mode, all frames are treated similarly.  
Semiconductor Group  
24  
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