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SAB82525N 参数 Datasheet PDF下载

SAB82525N图片预览
型号: SAB82525N
PDF下载: 下载PDF文件 查看货源
内容描述: 高层次的串行通信 [High-Level Serial Communication]
分类和应用: 通信
文件页数/大小: 126 页 / 741 K
品牌: SIEMENS [ Siemens Semiconductor Group ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
6
Special Functions  
6.1 Fully Transparent Transmission and Reception  
When programmed to the extended transparent mode via the MODE register (MDS1,  
MDS0 = 11), each channel of the HSCX supports fully transparent data transmission and  
reception without HDLC framing overhead, i.e. without  
FLAG insertion and deletion  
CRC generation and checking  
Bit-stuffing mechanism.  
In order to enable fully transparent data transfer, RAC bit in MODE has to be reset and FF  
has to be written to XAD1, XAD2 and RAH2.  
H
Data transmission is always performed out of the transmit FIFO by directly shifting the contents  
of the XFIFO via the serial transmit data pin (T×D). Transmission is initiated by setting  
CMDR : XTF (08 ); end of transmission is indicated by EXIR : EXE (40 ).  
H
H
In receive direction, the character currently assembled via the receive data line (R×D) is  
available in the RAL1 register. Additionally, in extended transparent mode 1 (MODE: MDS1,  
MDS0, ADM = 111), the received data is shifted into the RFIFO.  
This feature can be profitably used e.g. for:  
user specific protocol variations  
the application of character oriented protocols (e.g. BISYNC)  
test purposes, line intentionally violation of HDLC protocol rules (e.g. wrong CRC)  
Character synchronization can be achieved either in  
clock mode 1, with an external receive strobe input to A×CLK pin, or  
clock mode 5, with a programmed time-slot and a frame synchronization signal input to  
A × CLK.  
Using clock mode 1 or 5 multiples of 8 bits received per time-slot.  
6.2 Cyclic Transmission (Fully Transparent)  
If the extended transparent mode is selected, the HSCX supports the continuous transmission  
of the transmit FIFO’s contents.  
After having written 1 to 32 bytes to the XFIFO, the command  
XREP.XTF.XME  
via the CMDR register (bit 7. . .0 = "00101010" = 2AH) forces the HSCX to repeatedly transmit  
the data stored in the XFIFO via T×D pin.  
The cyclic transmission continues until a reset command (CMDR : XRES) is issued, after  
which continuous ’1’-s are transmitted.  
Note: In DMA-mode the command XREP, XTF has to be written to CMDR.  
Semiconductor Group  
65