SAB 82525
SAB 82526
SAF 82525
SAF 82526
8
Clock Recovery (DPLL)
In case the DPLL detects an edge in the data stream in the range of DPLL count 5 to 10 (Phase
Shift) and this is the only one in the assumed bit cell period, then the DPLL receive clock phase
is shifted by a certain DPLL count value. The DPLL value and its corresponding phase shift in
degree is listed below for the HSCX versions VA3 and V2.1:
HSCX Version
VA3
DPLL Count
Phase Shift
180 °
8
V2.1
7
157.5 °
Differences
Ver. A3
Ver. 2.1
tRD
tRR
tRI
tXDD1 min
tRTD1 min
tRTD2 min
tTCD min
100/110 ns
120 ns
60 ns
20 ns
30 ns
60/70 ns
70 ns
35 ns
10 ns
10 ns
10 ns
10 ns
20 ns
20 ns
Semiconductor Group
121
SIEMENS [ Siemens Semiconductor Group ]
