IRFR/U540Z
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W.
Period
V
GS
=10V
-
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
*
D.U.T. I
SD
Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V
DS
Waveform
Diode Recovery
dv/dt
-
-
+
R
G
•
•
•
•
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
V
DD
V
DD
+
-
Re-Applied
Voltage
Inductor Curent
Body Diode
Forward Drop
Ripple
≤
5%
I
SD
*
V
GS
= 5V for Logic Level Devices
Fig 17.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
R
D
V
DS
V
GS
R
G
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
D.U.T.
+
-
V
DD
Fig 18a.
Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 18b.
Switching Time Waveforms
8 / 11
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