TEST CIRCUITS (Cont.)
SGM4717
Rise Time Delay = |tINRISE–tOUTRISE
Fall Time Delay = |tINFALL–tOUTFALL
Rise Time to Fall Time Mismatch = |tOUTFALL–tOUTRISE
|
RS
NO1 or NC1
COM1
IN+
|
OUT+
OUT-
|
CL
IN1
RS
NO2 or NC2
COM2
IN-
IN2
CL
tINRISE
tINFALL
V
+
90%
10%
90%
10%
VIN+
50%
50%
0V
V
+
VIN-
0V
tINRISE
tINFALL
V
+
90%
90%
10%
VOUT+
50%
50%
10%
0V
V
+
ON
VOUT-
0V
tSKEW
Test Circuit 4. Output Signal Skew
V+
0.1µF
V+
NO or NC
COM
VOUT
CL
5pF
Source
Signal
IN
GND
Test Circuit 5. Off Isolation
7
SGM4717