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SC420AIMLTRT 参数 Datasheet PDF下载

SC420AIMLTRT图片预览
型号: SC420AIMLTRT
PDF下载: 下载PDF文件 查看货源
内容描述: 高速,组合式SenseTM ,为移动应用程序同步功率MOSFET驱动器 [High Speed, Combi-SenseTM, Synchronous Power MOSFET Driver for Mobile Applications]
分类和应用: 驱动器
文件页数/大小: 16 页 / 744 K
品牌: SEMTECH [ SEMTECH CORPORATION ]
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SC420A  
POWER MANAGEMENT  
Applications Information (Cont.)  
result, run the TG and BG connections with a  
minimum aspect ratio (length to width) of 20:1. This  
results in a 50 mil trace for a one inch connection.  
In addition, minimize the loop area of the gate drive  
loop. This is easy with BG, since the return path for  
the current is GND. In the case of TG, the return  
path for drivercurrent is DRN, so run these traces  
together, as closely as possible.  
Fig 3: Typical Layout schematic for SC420A  
Layout Guidelines  
As shown in the above layout the traces used for  
interconnections are not identical to each. The layout  
using the above traces has significant advantages.  
The traces used to interconnect C1, Dbst, Cbst, Rbst,  
Vcc, GND, and Vbat are wider and heavy. This is done to  
reduce the resistance and inductance of the current path.  
As a result the voltage drop of the traces is significantly  
reduced. This arrangement charges the Cbst capacitor  
faster. Because of this, the FET gate capacitances are  
also charged and discharged faster, improving the  
efficiency of the system. Ceramic X7R capacitors are a  
good choice for supply bypassing near the chip.  
Vias represent significant inductance and are to be  
avoided wherever possible. BG is especially important  
because when the HSFET switches off, the high dV/  
dt of the DRN node will force current into the LSFET  
gate via Cgd. A large inductance in the BG trace will  
prevent the driver from holding BG down at this time.  
The signal level traces are not critical because the  
current levels are much smaller.  
Wider traces are also used for TG and BG connects. This  
is essential to decrease the delay of signal through the  
trace and allow rapid charge and discharge of the FET  
capacitance. Inductance is usually the dominant  
impedance in the time range of interest (~10ns). As a  
We can also see vias (circular dots) present in the  
layout. The vias are important for interconnection  
between different layers of the PCB. Also they are  
important in heat transfer and aid in running the  
system cooler.  
2004 Semtech Corp.  
13  
United States Patent No. 6,441,597  
www.semtech.com