PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1182/3
August 25, 1998
as small as possible. This loop contains all the high
LAYOUT GUIDELINES
current, fast transition switching. Connections should
be as wide and as short as possible to minimize loop
inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in
electrically “cleaner” grounds for the rest of the system
and c) minimize source ringing, resulting in more reli-
able gate switching signals.
Careful attention to layout requirements are necessary
for successful implementation of the SC1182/3 PWM
controller. High currents switching at 200kHz are pre-
sent in the application and their effect on ground plane
voltage differentials must be understood and mini-
mized.
1). The high power parts of the circuit should be laid
out first. A ground plane should be used, the number
and position of ground plane interruptions should be
such as to not unnecessarily compromise ground plane
integrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the
input capacitor and bottom FET ground.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection
between the output inductor and the sense resistor
should be a wide trace or copper area, there are no
fast voltage or current transitions in this connection
and length is not so important, however adding unnec-
essary impedance will reduce efficiency.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
12V IN
5V
10
1
2
24
AGND
GATE1
LDOS1
LDOS2
VCC
GATE2
LDVO
VID0
23
22
21
20
19
18
17
16
15
14
13
2.32k
3
Cin
+
4
Q1
Q2
1.00k
VID1
0.1uF
0.1uF
5
5mOhm
VID2
Vout
6
OVP
VID3
4uH
+
7
P W R G O O D
CS-
VID4
Cout
8
VO SENSE
EN
9
CS+
10
11
12
PGNDH
DH
BSTH
BSTL
DL
PGNDL
SC1182/3
RA1
Heavy lines indicate
high current paths.
5V
Vo Lin1
Q3
+
+
RB1
Cout Lin1
Cin Lin
For SC1182, RA1, RA2, RB1 and RB2
are not required. LDOS1 connects to
Vo Lin1, LDOS2 connects to Vo Lin2
RA2
Vo Lin2
Q4
+
RB2
Cout Lin2
Layout diagram for the SC1182/3
8
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652 MITCHELL ROAD NEWBURY PARK CA 91320
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