Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description
Chip Overview
Grouping of DACs
The Edge6420 provides 64 output levels (44 voltage and DACs are separated into 4 channels of 6 distinct functional
20 current). These outputs can easily be configured to groups. Groups are defined by:
generate the specific analog voltage and current
requirements for 4 channels of ATE pin electronics
including:
– Type (voltage or current output)
– Resolution (# of bits)
– Output range
–
–
–
–
3 level driver
Window comparator
Active load
– Output compliance.
Per pin PMU
Table 1 defines the DACs on a per channel basis:
without requiring any scaling or shifting via external
components.
The Edge6420 has the flexibility to be used in other
configurations for other applications.
Programming of the chip is done using a 4 bit digital
interface comprised of:
–
–
–
–
Serial Data In
Clock
Update
Chip Enable.
Group
A
Group
B
Group
C
Group
D
Group
E
Group
F
Attribute
Total # of
DACs in Group
5 per channel
2 per channel
2 per channel
2 per channel
2 per channel
3 per channel
Type
V
V
V
V
I
I
Resolution
(# of bits)
13
13
13
13
13
6
Output Range:
Max DAC Range (Note 1)
Offset Range
11.5V
-3.5V to 2.5V
11.5V
-3.5V to 2.5V
17V
-3.5V to 2.5V
11.5V
-3.5V to 2.5V
3.6 mA
–128 LSB
(Note 2)
3.6 mA
0
Adjustable Output Offset
Compliance
yes
yes
yes
yes
no
no
± 100 µA
± 100 µA
± 100 µA
± 100 µA
–0.2 to AVDD – 2.2V –0.2 to AVDD – 2.2V
(Note 3) (Note 3)
Note 1: The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the
equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details.
Note 2: –128 LSB is equivalent to –128 * LSB, where LSB = Range / 213. For max range case of 3.6 mA,
this offset would thus be: –56.26 µA of offset current at Code 0.
Note 3: Compliance specified in the table is at IOUT = 1.3mA. Maximum compliance is lower at higher currents.
Please refer to specifications for compliance at other output currents.
Table 1. DAC Grouping
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