Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Digital Inputs
Set Up Times (Note 1)
SDI to Rising CK
T
10
10
5
ns
ns
ns
SU_SDI
CE (rising edge) to Rising CK24
UPDATE (rising edge) to Rising CK24
(Notes 2, 3)
T
SU_CE
T
70% of T
CK
SU_UPDT
Hold Times (Note 1)
SDI to Rising CK
T
10
10
5
ns
ns
ns
HLD_SDI
CE (falling edge) to Rising CK24
UPDATE (falling edge) to Rising CK24
(Notes 2, 3)
T
HLD_CE
T
70% of T
CK
HLD_UPDT
CK
Fmax at DVDD = 3.3V ± .30V (Notes 1,5)
30 to 50% Duty Cycle (Note 5)
70% Duty Cycle
F
max
33
20
MHz
MHz
Fmax at DVDD = 5.0V ± .50 (Notes 4,5)
30 to 50% Duty Cycle
70% Duty Cycle
F
max
55
35
MHz
MHz
Duty Cycle (Note 1)
RESET Pulse Width
PW
CK
30
2
50
70
%
PW
RESET
µs
Output Voltage Settling Time (Note 1)
(from CK Øcorresponding to UPDATE)
Full Scale Step, 10V (to 0.025% FSR)
for Groups A, B, D
Ts
Load: 10 nF
Load: 100 nF
30
250
70
700
µs
µs
Full Scale Step, 17V (to 0.025% FSR)
for Group C
Load: 10 nF
50
0.410
150
1
µs
ms
Load: 100 nF
Output Current Settling Time
Group E (to .025%)
Load: 1 nF
53
230
100
500
µs
µs
Load: 10 nF
Group F (to .8%)
Load: 1 nF
Load: 10 nF
4.4
29
10
50
µs
µs
Test conditions (unless otherwise specified): "Recommended Operating
Conditions".
CE
CK
T
SU_CE
T
CK
T
HLD_CE
Note: A 24th falling
CK edge is required for
DAC updating!
CK1
CK24
Note 1: Not production tested. Guaranteed by design and
characterization.
UPDATE
T
SU_UPDATE
Note 2: The max spec of 70% of T is not production tested.
CK
T
HLD_UPDATE
Note 3: CK24 refers to 24th rising clock edge, which corresponds
to a full shift register. Note that a falling CK24 edge is also
required for proper operation of circuit.
Note 4: The 6420 is production tested at 55 MHz only, with 50%
duty cycle.
Figure 9. Central and Individual DAC Updating
Valid Data
A0
Valid Data
D15
SDI
T
T
SU_SDI
SU_SDI
T
T
Note 5: Duty cycle % shown refers to “high” duration of clock
in a period.
HLD_SDI
HLD_SDI
CK
CK24
CK1
Figure 8. Shift Register Loading Timing Diagram
2000 Semtech Corp.
25
www .semtech.com