Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Current Outputs
The TEST_MODE and SCAN_OUT pins on the Edge6420 The typical "ON" resistance of the FET switch is 100 kΩ,
are used in the same way as for voltage outputs. The but can vary from 60 kΩ to 180 kΩ as a function of process
scan circuits for current outputs are shown in Figure 6.
and output voltage.
The voltage measured at the SCAN_OUT pin, using the Notes when Using SCAN Feature with Multiple Chips
configuration in Figure 6, for Group E and F current outputs
are as follows:
When multiple 6420s are used on a board, and it is desired
to gang the SCAN_OUT pins of these 6420s, or gang the
TEST_MODE inputs to one point, it is required for proper
functioning that the following rules be followed:
V
= (R
+ R ) * I
SCAN_OUT_E
SENSE_E PAD OUT_E
where:
1) If TEST_MODE inputs are ganged together,
SCAN_OUT cannot be ganged, or invalid results
will be observed at the SCAN_OUT pin. Hence,
each SCAN_OUT pin on a 6420 will have to be
measured separately.
R
= 400Ω ± 30%
= 30Ω ± 30%
SENSE_E
R
PAD
and
2) If SCAN_OUT is ganged, TEST_MODE pins cannot
be ganged together.
V
= (R
+ R ) * I
SCAN_OUT_F
SENSE_F PAD OUT_F
where:
R
= 400Ω ± 30%
SENSE_F
R
= 30Ω ± 30%
PAD
R
R
SENSE
PAD
+
IOUT_CH0_0
CONNECT TO
VIRTUAL GROUND
IDAC
–
TEST_MODE
R
R
SENSE
PAD
+
IOUT_CH0_1
CONNECT TO
VIRTUAL GROUND
IDAC
–
R
R
ADDRESS
DECODER
PAD
+
SENSE
IOUT_CH0_2
CONNECT TO
VIRTUAL GROUND
IDAC
–
SCAN_OUT
NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED.
Figure 6. Current Output Scan Circuits
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