E0C88861
s
BLOCK DIAGRAM
Core CPU E0C88
OSC1, 2
Oscillator
OSC3, 4
RESET
TEST
MNT0–MNT1
Interrupt Controller
Reset/Test
Input Port
K00–K07
K10 (EVIN)
Watchdog Timer
I/O Port
P14–P17
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
Clock Timer
Serial Interface
Stopwatch Timer
Programmable Timer
/Event Counter
R26 (TOUT
*)
R27 (TOUT)
V
DD
V
SS
V
D1
V
C1
–V
C5
CA–CG
Sound Generator
Power Generator
Output Port
R50 (BZ)
R51 (BZ
*)
∗
Selectable
by mask option
Supply Voltage Detector
LCD Driver
SEG0–SEG40
COM16–COM31 (SEG66–SEG51)
COM0–COM15
RAM
1.5KB
ROM
60KB
NOTICE:
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© Seiko Epson Corporation 1999 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ED International Marketing Department
I
(Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
ED International Marketing Department
II
(Asia)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5814 FAX : 042-587-5110
SEIKO [ SEIKO EPSON CORPORATION ]
