E0C88316
■ PIN DESCRIPTION
Pin name
Pin No.
In/Out
Function
V
V
V
V
DD
SS
D1
79
80
–
–
–
O
–
I
Power supply (+) terminal
Power supply (GND) terminal
78
Regulated voltage output terminal for oscillators
LCD drive voltage output terminals
C1–VC5
75–71
70–66
81
CA–CE
OSC1
Booster capacitor connection terminals for LCD
OSC1 oscillation input terminal
(select crystal oscillation/CR oscillation/external clock input with mask option)
OSC1 oscillation output terminal
OSC2
OSC3
82
76
O
I
OSC3 oscillation input terminal
(select crystal/ceramic/CR oscillation/external clock input with mask option)
OSC3 oscillation output terminal
OSC4
77
85
O
I
MCU/MPU
K00–K07
Terminal for setting MCU or MPU modes
95–88
87
I
Input terminals (K00–K07)
K10/EVIN
I
Input terminal (K10) or event counter external clock input terminal (EVIN)
Input terminal (K11) or bus request signal input terminal (BREQ)
Output terminals (R00–R07) or address bus (A0–A7)
Output terminals (R10–R17) or address bus (A8–A15)
Output terminals (R20–R22) or address bus (A16–A18)
Output terminal (R23) or read signal output terminal (RD)
Output terminal (R24) or write signal output terminal (WR)
Output terminal (R25) or LCD synchronous signal output terminal (CL)
Output terminal (R26) or LCD frame signal output terminal (FR)
Output terminal (R27)
K11/BREQ
R00–R07/A0–A7
R10–R17/A8–A15
R20–R22/A16–A18
R23/RD
86
I
112–119
120–127
128–130
131
O
O
O
O
O
O
O
O
R24/WR
132
R25/CL
133
R26/FR
134
R27/TOUT
135
or programmable timer underflow signal output terminal (TOUT)
Output terminals (R30–R33) or chip enable output terminals (CE0–CE3)
Output terminal (R34) or clock output terminal (FOUT)
Output terminals (R35–R37)
R30–R33/CE0–CE3
R34/FOUT
136–139
140
O
O
R35–R37
2
O
R50/BZ
141
142
O
Output terminal (R50) or buzzer output terminal (BZ)
Output terminal (R51) or bus acknowledge signal output terminal (BACK)
I/O terminals (P00–P07) or data bus (D0–D7)
R51/BACK
P00–P07/D0–D7
P10/SIN
O
111–104
103
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O terminal (P10) or serial I/F data input terminal (SIN)
I/O terminal (P11) or serial I/F data output terminal (SOUT)
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O terminal (P14) or comparator 0 non-inverted input terminal
I/O terminal (P15) or comparator 0 inverted input terminal
I/O terminal (P16) or comparator 1 non-inverted input terminal
I/O terminal (P17) or comparator 1 inverted input terminal
LCD common output terminals
P11/SOUT
P12/SCLK
102
101
P13/SRDY
P14/CMPP0
P15/CMPM0
P16/CMPP1
P17/CMPM1
COM0–COM15
COM16–COM31
/SEG66–SEG51
SEG0–SEG50
RESET
100
99
98
97
96
65–50
49–34
O
LCD common output terminals (when 1/32 duty is selected)
or LCD segment output terminal (when 1/16 or 1/8 duty is selected)
LCD segment output terminals
143–160, 1–33
O
I
84
83
Initial reset input terminal
TEST
1
I
Test input terminal
1 TEST is the terminal used for shipping inspection of the IC. For normal operation be sure it is connected to VDD
.
2 R35–R37 terminals can be used only when the E0C88316 chip is being shipped.
4
SEIKO [ SEIKO EPSON CORPORATION ]
