E0C88316
s
PIN DESCRIPTION
Pin name
V
DD
V
SS
V
D1
V
C1
–V
C5
CA–CE
OSC1
OSC2
OSC3
OSC4
MCU/MPU
K00–K07
K10/EVIN
K11/BREQ
R00–R07/A0–A7
R10–R17/A8–A15
R20–R22/A16–A18
R23/RD
R24/WR
R25/CL
R26/FR
R27/TOUT
Pin No.
79
80
78
75–71
70–66
81
82
76
77
85
95–88
87
86
112–119
120–127
128–130
131
132
133
134
135
In/Out
–
–
–
O
–
I
O
I
O
I
I
I
I
O
O
O
O
O
O
O
O
Function
Power supply (+) terminal
Power supply (GND) terminal
Regulated voltage output terminal for oscillators
LCD drive voltage output terminals
Booster capacitor connection terminals for LCD
OSC1 oscillation input terminal
(select crystal oscillation/CR oscillation/external clock input with mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal
(select crystal/ceramic/CR oscillation/external clock input with mask option)
OSC3 oscillation output terminal
Terminal for setting MCU or MPU modes
Input terminals (K00–K07)
Input terminal (K10) or event counter external clock input terminal (EVIN)
Input terminal (K11) or bus request signal input terminal (BREQ)
Output terminals (R00–R07) or address bus (A0–A7)
Output terminals (R10–R17) or address bus (A8–A15)
Output terminals (R20–R22) or address bus (A16–A18)
Output terminal (R23) or read signal output terminal (RD)
Output terminal (R24) or write signal output terminal (WR)
Output terminal (R25) or LCD synchronous signal output terminal (CL)
Output terminal (R26) or LCD frame signal output terminal (FR)
Output terminal (R27)
or programmable timer underflow signal output terminal (TOUT)
Output terminals (R30–R33) or chip enable output terminals (CE0–CE3)
Output terminal (R34) or clock output terminal (FOUT)
Output terminals (R35–R37)
Output terminal (R50) or buzzer output terminal (BZ)
Output terminal (R51) or bus acknowledge signal output terminal (BACK)
I/O terminals (P00–P07) or data bus (D0–D7)
I/O terminal (P10) or serial I/F data input terminal (SIN)
I/O terminal (P11) or serial I/F data output terminal (SOUT)
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O terminal (P14) or comparator 0 non-inverted input terminal
I/O terminal (P15) or comparator 0 inverted input terminal
I/O terminal (P16) or comparator 1 non-inverted input terminal
I/O terminal (P17) or comparator 1 inverted input terminal
LCD common output terminals
LCD common output terminals (when 1/32 duty is selected)
or LCD segment output terminal (when 1/16 or 1/8 duty is selected)
LCD segment output terminals
Initial reset input terminal
Test input terminal
136–139
O
R30–R33/CE0–CE3
140
O
R34/FOUT
O
R35–R37
∗2
141
O
R50/BZ
142
O
R51/BACK
111–104
I/O
P00–P07/D0–D7
103
I/O
P10/SIN
102
I/O
P11/SOUT
101
I/O
P12/SCLK
100
I/O
P13/SRDY
99
I/O
P14/CMPP0
98
I/O
P15/CMPM0
97
I/O
P16/CMPP1
96
I/O
P17/CMPM1
65–50
O
COM0–COM15
49–34
O
COM16–COM31
/SEG66–SEG51
143–160, 1–33
O
SEG0–SEG50
84
I
RESET
83
I
TEST
∗1
∗1
TEST is the terminal used for shipping inspection of the IC. For normal operation be sure it is connected to V
DD
.
∗2
R35–R37 terminals can be used only when the E0C88316 chip is being shipped.
4
SEIKO [ SEIKO EPSON CORPORATION ]
