E0C88112
s
BLOCK DIAGRAM
Core CPU E0C88
OSC1, 2
Oscillator
OSC3, 4
MCU/MPU
BREQ (K11)
BACK (R51)
RESET
Interrupt Controller
K00–K07
K10 (EVIN)
K11 (BREQ)
System Controller
Input Port
Reset/Test
TEST
I/O Port
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P14, P15 (CMPP0, CMPM0)
P16, P17 (CMPP1, CMPM1)
P00–P07 (D0–D7)
R00–R07, R10–R17, R20–R22 (A0–A7, A8–A15, A16–A18)
R23, R24 (RD, WR)
R30–R33 (CE0–CE3)
R25, R26
R27 (TOUT)
R34 (FOUT)
R35–R37
R50 (BZ)
R51 (BACK)
Watchdog Timer
Serial Interface
EVIN (K10)
Programmable Timer
/Event Counter
Analog
Comparator
Clock Timer
External
Memory
Interface
Stopwatch Timer
Sound Generator
V
DD
V
SS
V
D1
Power Generator
Output Port
Supply Voltage Detector
RAM
256 byte
ROM
12K byte
s
PIN CONFIGURATION
QFP14-80pin
60
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
61
E0C88112
INDEX
80
1
R00/A0
1
21
R24/WR
41
R50/BZ
61
RESET
R01/A1
2
22
R25
42
R51/BACK
62
N.C.
41
R02/A2
3
23
R26
43
P17/CMPM1
63
K11/BREQ
R03/A3
4
24
R27/TOUT
44
P16/CMPP1
64
K10/EVIN
R04/A4
5
25
R30/CE0
45
P15/CMPM0
65
K07
40
R05/A5
6
26
R31/CE1
46
P14/CMPP0
66
K06
R06/A6
7
27
R32/CE2
47
P13/SRDY
67
K05
R07/A7
8
28
R33/CE3
48
P12/SCLK
68
K04
R10/A8
9
29
R34/FOUT
49
P11/SOUT
69
K03
10
R11/A9
30
R35
50
P10/SIN
70
K02
11
R12/A10
31
R36
51
P07/D7
71
K01
12
R13/A11
32
R37
52
P06/D6
72
K00
13
R14/A12
33
∗
53
P05/D5
73
MCU/MPU
14
R15/A13
34
∗
54
P04/D4
74
V
DD
15
R16/A14
35
∗
55
P03/D3
75
OSC4
16
R17/A15
36
∗
56
P02/D2
76
OSC3
21
17
R20/A16
37
∗
57
P01/D1
77
V
D1
18
R21/A17
38
∗
58
P00/D0
78
OSC2
19
R22/A18
39
∗
59
N.C.
79
OSC1
20
20
R23/RD
40
∗
60
TEST
80
V
SS
∗
Pins No. 33 to 40 are the pads used for outgoing inspection of the IC. Do not connect anything to these pins.
N.C. : No Connection
2
SEIKO [ SEIKO EPSON CORPORATION ]
