E0C6S46
s
PIN CONFIGURATION
QFP5-128pin
102
103
65
64
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
V
L3
V
L4
V
L5
CF
N.C.
CE
CD
CC
CB
CA
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
SEG33
N.C.
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Pin name No. Pin name
SEG2
97 R42
SEG1
98 N.C.
SEG0
99 R41
SCLK
100 R40
N.C.
101 R33
SOUT
102 R32
SIN
103 R31
K13
104 R30
K12
105 R23
K11
106 R22
K10
107 R21
K03
108 R20
K02
109 R13
K01
110 R12
K00
111 R11
P33
112 R10
P32
113 R03
P31
114 R02
P30
115 R01
P23
116 R00
P22
117 V
SS
P21
118 RESET
P20
119 TEST
P13
120 OSC4
P12
121 OSC3
P11
122 V
S1
P10
123 OSC2
P03
124 OSC1
P02
125 V
DD
P01
126 V
REF
P00
127 V
L1
R43
128 V
L2
N.C. = No Connection
E0C6S46
INDEX
128
39
1
38
s
PIN DESCRIPTION
Pin name
V
DD
V
SS
V
S1
V
L1
–V
L5
Pin No.
125
117
122
127, 128, 1–3
I/O
–
–
–
–
126
O
V
REF
10–6, 4
–
CA–CF
124
I
OSC1
123
O
OSC2
121
I
OSC3
120
O
OSC4
11–26
O
COM0–COM15
67–35, 33–27
O
SEG0–SEG39
79–76
I
K00–K03
75–72
I
K10–K13
95–92
I/O
P00–P03
91–88
I/O
P10–P13
87–84
I/O
P20–P23
83–80
I/O
P30–P33
116–113
O
R00–R03
112–109
O
R10–R13
108–105
O
R20–R23
104–102
O
R30–R32
101
O
R33
100
O
R40
99
O
R41
97
O
R42
96
O
R43
71
I
SIN
70
O
SOUT
68
I/O
SCLK
118
I
RESET
119
I
TEST
∗1
Selected by mask option
∗2
Leave the V
REF
pin unconnected (N.C.).
∗3
The TEST pin is used when the IC load is being detected. During ordinary operation be certain to connect this pin to V
DD
.
Function
Power supply (+)
Power supply (-)
Internal logic system/oscillation system regulated voltage output
LCD system power supply
1/4 bias generated internally, 1/5 bias generated externally
∗
1
LCD system power test pin
∗
2
LCD system voltage booster condenser connecting pin
Crystal oscillator input
Crystal oscillator output, C
D
buiil-in
CR or ceramic oscillator input
∗
1
CR or ceramic oscillator output
∗
1
LCD common output (1/8 duty or 1/16 duty is selected on software)
LCD segment output
Input port (pull up resistor is available by mask option)
∗
1
Input port (pull up resistor is available by mask option)
∗
1
I/O port
Complementary output or
I/O port
Nch open drain output
∗
1
I/O port
I/O port or output port
∗
1
Output port
Output port
Output port
Output port
Output port, SRDY output or PTCLK output
∗
1
Output port or FOUT output
∗
1
Output port
Output port, BZ output or FOUT output
∗
1
Output port or BZ output
∗
1
Serial interface data input
Serial interface data output
Serial interface clock input/output
Initial reset input terminal
Testing input terminal
∗
3
3
SEIKO [ SEIKO EPSON CORPORATION ]
