E0C63P366
■ BASIC EXTERNAL CONNECTION DIAGRAM
LCD panel 32 × 4
When used as the E0C63358
(Leave OPEN when used as the E0C63158)
Input
K00–K03
K10–K13
K20
CA
CB
AVDD
AVREF
TEST
C1
P00–P03
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P20–P23
VDD
+
CP
C2
VD1
I/O
C
GX
OSC1
OSC2
OSC3
OSC4
RESET
P30–P33
2.7 V
|
X'tal
P40 (AD0)
P41 (AD1)
P42 (AD2)
P43 (AD3)
E0C63P366
[The potential of the substrate
(back of the chip) is VSS.]
1
5.5 V
C
GC
DC
CR
C
R00
3
2
R01
Output
R02 (TOUT)
R03 (FOUT)
R10–R13
R20–R23
CRES
V
AVSS
SS
Exclusive cable
1 VSS
2 TXD
3 RXD
4 CLK
SPRG
TXD
RXD
CLKIN
SCLK
5 SCLK
6 VSS
1: Crystal oscillation
2: CR oscillation
7 CLKW
8 VPP
3: Ceramic oscillation
Piezo
Coil
Exclusive
PROM writer
X'tal
Crystal oscillator
32.768 kHz, CI (Max.) = 34 kΩ
C
CR
GX
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation 91 kΩ (1.8 MHz/3.0 V)
Capacitor
Capacitor
RESET terminal capacitor
5–25 pF
4 MHz (3.0 V)
100 pF
C
C
R
C
C
C
GC
DC
CR
100 pF
1
–C
5
0.2 µF
3.3 µF
0.1 µF
P
RES
Note: The above table is simply an example, and is not guaranteed to work.
17
SEIKO [ SEIKO EPSON CORPORATION ]
