E0C63P366
3) Power supply terminal for the oscillation circuit (V
D1
)
The V
D1
voltage that is generated by the internal voltage regulator is used only for the OSC1 oscillation circuit
to stabilize the oscillation. As explained in Item 1 above, the VDC register (FF00H•D0) does not affect the V
D1
output voltage.
4) Operating mode of LCD system voltage regulator
The operable voltage range is different.
E0C63358: V
DD
= 0.9V to 1.4V V
C1
= V
DD
V
DD
= 1.4V to 3.6V V
C1
= 1.05V (Typ.)
E0C63P366: V
DD
= 2.7V to 5.5V
V
C2
= 2.10V (Typ.)
∗
The E0C63P366 operation is guaranteed within the above voltage range.
5) Operating mode of A/D converter power supply
The A/D converter operating mode range of the E0C63P366 is different from that of the E0C63358 and
E0C63158 because the operable voltage range is different.
E0C63158
Circuit
A/D converter
E0C63358
Circuit
A/D converter
E0C63P366
Circuit
A/D converter
Supply voltage V
DD
(V)
0.9–2.7
2.7–3.6
3.6–5.5
Not allowed
Normal mode
Supply voltage V
DD
(V)
0.9–1.6
1.6–3.6
3.6–5.5
V
C2
mode Normal mode Not allowed
Supply voltage V
DD
(V)
0.9–2.2
2.2–3.6
3.6–5.5
V
C2
mode Normal mode Not allowed
q
Initial Reset
When the power is turned on, the reset terminal must be set at Low level until the supply voltage becomes 2.7V
or more.
2.7 V
V
DD
2.0 msec or more
RESET
Power on
0.5•V
DD
0.1•V
DD
or less (low level)
E0C63P366 uses the initial reset signal as a trigger for setting either the normal operation mode or the program-
ming mode. Therefore, design the reset input circuit so that the IC will be reset for sure. Initial resetting during
operation is the same as the E0C63158.
When resetting the IC in the normal operation mode, make sure to fix the SPRG terminal at High level.
q
ROM, RAM
The E0C63P366 employs a Flash EEPROM for the internal ROM. The Flash EEPROM can be rewritten up to 10
times. Rewriting data is done at the user's own risk.
1) Code ROM
The built-in code ROM is a Flash ROM for loading programs, and has a capacity of 16,384 steps
×
13 bits.
The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the
program area of the E0C63P366 is step 0000H to step 3FFFH. The program start address after initial reset is
assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allo-
cated to step 0100H and steps 0102H–010EH, respectively.
8
SEIKO [ SEIKO EPSON CORPORATION ]
