PF1005-02
E0C63B07
4-bit Single Chip Microcomputer
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oltan
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ow ratio s
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Op oduc
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4-bit Low Cycle / Inst. Core CPU
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Built-in 7 Segment Type LCD Driver
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Low Voltage Operation (0.9V Min.)
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Built-in Gate Array
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DESCRIPTION
The E0C63B07 is a CMOS 4-bit microcomputer composed of a CMOS 4-bit core CPU, ROM, RAM, 7 segment
type LCD driver, 10000 gates of gate array and counters. And the E0C63B07 can be operated by single Manga-
nese battery with LCD display. So that tha E0C63B07 is best suited for systems such as numeric pager.
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FEATURES
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CMOS LSI 4-bit parallel processing
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OSC1 oscillation circuit ......................... 32.768/76.8/153.6kHz (Typ.) Crystal oscillation circuit (∗1)
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OSC3 oscillation circuit ......................... 400kHz (Max.) CR oscillation circuit, Operatable in 0.9V
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Instruction set ........................................ Basic instruction : 46 types (411 instructions with all)
Addressing mode : 8 types
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Instruction execution time ..................... During operation at 32.768kHz : 61µsec
During operation at 76.8kHz : 26µsec
During operation at 153.6kHz : 13µsec
During operation at 400kHz
: 5µsec
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ROM capacity ....................................... Code ROM: 8,192 words
×
13 bits
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RAM capacity ........................................ Data memory
: 1,024 words
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4 bits
Display memory : 60 words
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4 bits
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Input port ............................................... 8 bits (Pull-up resistors may be supplemented
∗1)
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Output port ............................................ 8 bits (It is possible to switch the 2 bits to special output
∗2)
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I/O port .................................................. 12 bits (It is possible to switch the 4 bits to serial input/output *2)
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Serial interface ...................................... 1 port (8-bit clock synchronous system)
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LCD driver ............................................. 60 segments
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4, 3 or 2 commons (∗2) 1/3 or 1/2 bias drive (∗1)
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Time base counter ................................ 2 systems (Clock timer, stopwatch timer)
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Programmable timer ............................. Built-in, 2 inputs
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8 bits, with event counter function
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Watchdog timer ..................................... Built-in
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Gate array ............................................. SOG
Number of terminals
CPU interface
: 10,000 gates
: 28 bits
: Bus interface
122µsec
52µsec
26µsec
10µsec
183µsec
78µsec
39µsec
15µsec
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Melody generator .................................. Equivalent to SVM7100M Series
Maximum 16 melodies
Melody ROM capacity : 495 words
(words can be optionally arranged for each melody)
Address control ROM : 80 words
(words can be optionally arranged for each melody)
Play output waveform : Single sound square wave
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Supply voltage detection (SVD) circuit .. 16 values, programmable (1.05V to 2.60V)
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External interrupt .................................. Input port interrupt : 2 systems
SEIKO EPSON CORPORATION
1
SEIKO [ SEIKO EPSON CORPORATION ]
