E0C63557
<Master mode>
SCLK OUT
V
OH
V
OL
t
smd
SOUT
V
OH
V
OL
t
sms
SIN
V
IH1
V
IL1
t
smh
<Slave mode>
SCLK IN
V
IH1
V
IL1
t
ssd
SOUT
V
OH
V
OL
t
sss
SIN
V
IH1
V
IL1
t
ssh
Asynchronous System
(Condition: V
DD
=2.2 to 5.5V, V
SS
=0V, Ta=-20 to 70°C)
Characteristic
Min.
Typ.
Max.
Unit
Symbol
∗
1
Start bit detection error time
t
sa
1
0
t
/16
S
Erroneous start bit detection range time
∗
2
t
sa
2
9
t
/16
10
t
/16
S
∗1:
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
∗2:
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit detection
circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.)
Start bit
SIN
Stop bit
t
sa
1
Sampling
clock
t
Erroneous
start bit
detection signal
t
sa
2
q
Timing Chart
System clock switching
OSCC
5 msec min.
CLKCHG
1 instruction execution
time or longer
8
SEIKO [ SEIKO EPSON CORPORATION ]
