E0C63467
I BASIC EXTERNAL CONNECTION DIAGRAM
• When negative polarity is selected for buzzer output (mask option selection)
LCD panel 60 × 9
SVD
CA
CB
CC
CD
CE
C1
C2
C3
Input
K00–K03
K10–K13
CF
P00–P03
TEST
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P20–P23
V
DD
+
I/O
C
P
C
4
VD1
C9
E0C63467
[The potential of the substrate
(back of the chip) is VSS.]
VREF
CGX
P30–P32
P33 (SVD)
OSC1
OSC2
OSC3
OSC4
RESET
(1.2 V)
2.2 V
|
X'tal
∗1
3.6 V
Output
R00–R02
R03 (FOUT)
CGC
CR
CDC
∗3
∗2
CRES
V
SS
∗1: Crystal oscillation
∗2: CR oscillation (external R type)
∗3: Ceramic oscillation
Piezo
Coil
X'tal
Crystal oscillator
32.768 kHz, CI (Max.) = 34 kΩ
C
CR
GX
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation 47 kΩ (1.8 MHz)
Capacitor
Capacitor
Capacitor
RESET terminal capacitor
5–25 pF
4 MHz (3.0 V)
30 pF
C
C
R
C
C
C
C
GC
DC
30 pF
CR2
1
–C
8
0.2 µF
0.1 µF
3.3 µF
0.1 µF
9
P
RES
Notes: • The above table is simply an example, and is not guaranteed to work.
• In order to prevent unstable operation of the OSC3 oscillation circuit due to current leak between OSC3
and VDD, please keep enough distance between VDD and other signals on the board pattern.
• In order to get a stable frequency for ceramic oscillation, please use maker's recommendatory value for
CGC and CDC.
12
SEIKO [ SEIKO EPSON CORPORATION ]
