E0C63466
■ BASIC EXTERNAL CONNECTION DIAGRAM
LCD panel 60 × 17
SVD
CA
CB
CC
CD
CE
CF
TEST
Input
C1
C2
C3
K00–K03
K10–K13
P00–P03
P10 (SIN)
P11 (SOUT)
I/O
P12 (SCLK)
VDD
+
P13 (SRDY)
P20
P21
P22 (CL)
P23 (FR)
C
P
C
4
V
VREF
D1
C9
E0C63466
[The potential of the substrate
CGX
OSC1
OSC2
OSC3
OSC4
RESET
(1.8 V)
2.2 V
|
(back of the chip) is VSS.]
X'tal
R00
R01
R02 (TOUT)
R03 (FOUT)
R10–R13
1
2
6.4 V
Output
C
GC
DC
CR
C
3
2
R20–R23
CRES
V
SS
1: Crystal oscillation
2: CR oscillation
3: Ceramic oscillation
Piezo
Coil
X'tal
Crystal oscillator
Trimmer capacitor
32.768 kHz, C
5–25 pF
I (Max.) = 34 kΩ
CGX
RCR1
Resistor for OSC1 CR oscillation 600 kΩ (60 kHz)
CR
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation 47 kΩ (1.8 MHz)
Capacitor
Capacitor
Capacitor
RESET terminal capacitor
4 MHz (3.0 V)
30 pF
30 pF
C
C
R
C
C
C
C
GC
DC
CR2
1–C
8
0.2 µF
0.1 µF
3.3 µF
0.1 µF
9
Note: The above table is simply
an example, and is not
guaranteed to work.
P
RES
9
SEIKO [ SEIKO EPSON CORPORATION ]
