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E0C6251F 参数 Datasheet PDF下载

E0C6251F图片预览
型号: E0C6251F
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64]
分类和应用: 时钟外围集成电路
文件页数/大小: 9 页 / 98 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C6251
E0C6251 (CR, Normal Mode)
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC
=65kHz, R
CR
=420kΩ, Ta=25°C, V
S1
/V
L1
–V
L3
are internal voltage, C1–C6=0.1µF)
(During A/D conversion: RS=49.8kΩ, TH=50kΩ, CS=2,200pF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal voltage
V
L1
Connect 1MΩ load resistor between V
DD
and V
L1
-1.15
-1.05
-0.95
V
(without panel load)
V
L2
Connect 1MΩ load resistor between V
DD
and V
L2
2•V
L1
2•V
L1
V
(without panel load)
-0.1
×0.9
V
L3
Connect 1MΩ load resistor between V
DD
and V
L3
3•V
L1
3•V
L1
V
(without panel load)
-0.1
×0.9
SVD voltage
V
SVD
-2.55
-2.40
-2.25
V
SVD circuit response time
t
SVD
100
µS
Current consumption
I
OP
During HALT
8.0
15.0
µA
During execution
*
1
Without panel load
15.0
20.0
µA
During A/D conversion (HALT)
37
52.5
µA
∗1:
The SVD circuit is turned off.
E0C6251 (CR, Heavy Load Protection Mode)
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC
=65kHz, R
CR
=420kΩ, Ta=25°C, V
S1
/V
L1
–V
L3
are internal voltage, C1–C6=0.1µF)
(During A/D conversion: RS=49.8kΩ, TH=50kΩ, CS=2,200pF)
Characteristic
Symbol
Condition
Min.
Typ.
Unit
Max.
Internal voltage
V
L1
Connect 1MΩ load resistor between V
DD
and V
L1
-1.15
-1.05
-0.95
V
(without panel load)
V
L2
Connect 1MΩ load resistor between V
DD
and V
L2
2•V
L1
2•V
L1
V
(without panel load)
-0.1
×0.85
V
L3
Connect 1MΩ load resistor between V
DD
and V
L3
3•V
L1
3•V
L1
V
(without panel load)
-0.1
×0.85
SVD voltage
V
SVD
-2.55
-2.40
-2.25
V
SVD circuit response time
t
SVD
100
µS
Current consumption
I
OP
During HALT
16.0
30.0
µA
During execution
*
1
Without panel load
30.0
40.0
µA
During A/D conversion (HALT)
45
57.5
µA
∗1:
The SVD circuit is turned off.
E0C62L51 (CR, Normal Mode)
(Unless otherwise specified: V
DD
=0V, V
SS
=-1.5V, f
OSC
=65kHz, R
CR
=420kΩ, Ta=25°C, V
S1
/V
L1
–V
L3
are internal voltage, C1–C6=0.1µF)
(During A/D conversion: RS=49.8kΩ, TH=50kΩ, CS=2,200pF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal voltage
V
L1
Connect 1MΩ load resistor between V
DD
and V
L1
-1.15
-1.05
-0.95
V
(without panel load)
V
L2
Connect 1MΩ load resistor between V
DD
and V
L2
2•V
L1
2•V
L1
V
(without panel load)
-0.1
×0.9
V
L3
Connect 1MΩ load resistor between V
DD
and V
L3
3•V
L1
3•V
L1
V
(without panel load)
-0.1
×0.9
SVD voltage
V
SVD
-1.30
-1.20
-1.10
V
SVD circuit response time
t
SVD
100
µS
Current consumption
I
OP
During HALT
8.0
15.0
µA
During execution
*
1
Without panel load
15.0
20.0
µA
During A/D conversion (HALT)
37
52.5
µA
∗1:
The SVD circuit is turned off.
E0C62L51 (CR, Heavy Load Protection Mode)
(Unless otherwise specified: V
DD
=0V, V
SS
=-1.5V, f
OSC
=65kHz, R
CR
=420kΩ, Ta=25°C, V
S1
/V
L1
–V
L3
are internal voltage, C1–C6=0.1µF)
(During A/D conversion: RS=49.8kΩ, TH=50kΩ, CS=2,200pF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal voltage
V
L1
Connect 1MΩ load resistor between V
DD
and V
L1
-1.15
-1.05
-0.95
V
(without panel load)
V
L2
Connect 1MΩ load resistor between V
DD
and V
L2
2•V
L1
2•V
L1
V
(without panel load)
-0.1
×0.85
V
L3
Connect 1MΩ load resistor between V
DD
and V
L3
3•V
L1
3•V
L1
V
(without panel load)
-0.1
×0.85
SVD voltage
V
SVD
-1.30
-1.20
-1.10
V
SVD circuit response time
t
SVD
100
µS
Current consumption
I
OP
During HALT
16.0
30.0
µA
During execution
*
1
Without panel load
30.0
40.0
µA
During A/D conversion (HALT)
45
57.5
µA
∗1:
The SVD circuit is turned off.
6