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E0C60L03D 参数 Datasheet PDF下载

E0C60L03D图片预览
型号: E0C60L03D
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, 0.08MHz, MICROCONTROLLER, UUC36, DIE-36]
分类和应用: 时钟外围集成电路
文件页数/大小: 8 页 / 64 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C6003
s
BLOCK DIAGRAM
ROM
768 words
×
12 bits
System Reset
Control
RESET
Core CPU E0C6200B
OSC1
OSC2
OSC
Interrupt
Generator
K00–K03
RAM
64 words
×
4 bits
Input Port
TEST
R00 (FOUT, BUZZER)
∗1
R01 (BUZZER)
∗1
R02, R03
COM0–3
SEG0–14
LCD Driver
15 SEG
×
4 COM
Output Port
FOUT
& Buzzer
V
DD
CA, CB
V
S2
V
SS
Power
Controller
Clock
Timer
∗1:
Terminal specifications can be selected by mask option.
s
PAD LAYOUT
Pad Layout Diagram
15
10
5
1
Y
35
(0, 0)
X
30
Die No.
20
25
2.03 mm
2.32 mm
Chip thickness: 400µm
Pad opening: 95µm
Pad Coordinates
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pad name
TEST
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
X
980
850
720
590
460
330
200
70
-60
-190
-320
-450
Y
849
849
849
849
849
849
849
849
849
849
849
849
No.
13
14
15
16
17
18
19
20
21
22
23
24
Pad name
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
CA
CB
V
S2
V
SS
X
-580
-710
-840
-970
-983
-853
-723
-593
-463
-333
-203
-50
Y
849
849
849
849
-849
-849
-849
-849
-849
-849
-849
-849
No.
25
26
27
28
29
30
31
32
33
34
35
36
Pad name
OSC2
OSC1
V
DD
RESET
R00
R01
R02
R03
K00
K01
K02
K03
X
80
210
340
470
994
994
994
994
994
994
994
994
Y
-849
-849
-849
-849
-760
-542
-403
-269
-120
10
140
270
2