5036 series
PAD LAYOUT
(Unit:
µ
m)
OUT OUTN VCC2 OE
8
7
6
5
(550, 650)
Y
TEST
9
(0,0)
1
2
3
4
(−550,
−650)
VCC
XIN XOUT GND
X
Chip size: 1.10
×
1.30mm
Chip thickness: 300 ± 30µm, 180 ± 20µm
PAD size: 150µm
×
100µm (VCC, OUT, OUTN pins)
100µm
×
100µm (excluding VCC, OUT, OUTN pins)
Chip base: GND potential
Note: The TEST pin is not used during normal operation.
PIN DESCRIPTION and PAD DIMENSIONS
Pad No.
1
2
3
4
5
6
7
8
9
Name
VCC
XIN
XOUT
GND
OE
VCC2
OUTN
OUT
TEST
I/O
*1
–
I
O
–
I
–
O
O
–
(+) supply pin
Oscillator input pin
Oscillator output pin
(–) ground pin
Output enable pin. Outputs are high impedance when LOW (oscillator
stopped). Power-saving pull-up resistor built-in.
(+) output buffer supply pin
Complementary output pin
Output pin
IC test pin. Leave open circuit for normal operation.
Pad dimensions [µm]
Function
X
–390
–39
190
415
346
209
–27
–306
–414
Y
–520
–520
–520
–520
520
520
520
520
28
*1. I: input, O: output
BLOCK DIAGRAM
VCC
XIN
Colpitts
OSC
1/2
LV-PECL
VCC2
OUT
OUTN
XOUT
OE
GND
SEIKO NPC CORPORATION —2
SEIKO [ SEIKO EPSON CORPORATION ]
