A1225, A1227
and A1229
Hall Effect Latch for High Temperature Operation
Package LT 3-Pin SOT-89
+0.13
–0.08
4.47
1.73 ±0.10
E
2.50
2.00
+0.03
–0.06
0.41
2.24
B
0.38 MIN
D
0.80
E
1.14
6° REF
2.60
1.20
Parting Line
+0.03
–0.28
2.57
2.16 REF
+0.10
–0.20
4.14
4.60
10° REF
2
1
3
1.04 ±0.15
1.50
PCB Layout Reference View
0.70
C
Branded Face
10° REF
+0.05
Basic pads for low-stress, not self-aligning
Additional pad for low-stress, self-aligning
Additional area for IPC reference layout
+0.15
–0.05
1.45
0.43
–0.07
+0.05
–0.07
0.51
NN
2X 1.50 NOM
1
Standard Branding Reference View
A
= Supplier emblem
N = Last two digits of device part number
Updated package drawing only. Allegro package assembly tooling has not changed.
For Reference Only; not for tooling use (reference DWG-9064)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Branding scale and appearance at supplier discretion
Gate and tie bar burr area
B
C
Reference land pattern layout;
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances
Active Area Depth, 0.77 mm
D
E
Hall element; not to scale
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com