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S5PV210AA0-LA40 参数 Datasheet PDF下载

S5PV210AA0-LA40图片预览
型号: S5PV210AA0-LA40
PDF下载: 下载PDF文件 查看货源
内容描述: RISC微处理器, S5PV210是一个32位RISC成本效益,低功耗,移动电话和一般应用的高性能的微处理器解决方案,并集成了ARM Cortex- A8 ,它实现了ARM体系结构v7 -A与支持众多外设。 [RISC Microprocessor,S5PV210 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones and general applications, and integrates an ARM Cortex-A8 which implements the ARM architecture V7-A with supporting numerous peripherals.]
分类和应用: 微处理器移动电话
文件页数/大小: 17 页 / 1871 K
品牌: SAMSUNG [ SAMSUNG ]
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Tel:021-58998693  
S5PV210AA0-LA40  
Supports 14x8 key matrix  
10-channel 12-bit multiplexed ADC  
Configurable GPIOs  
Real time clock, PLL, timer with PWM and watch dog timer  
System timer support for accurate tick time in power down mode except sleep mode  
Memory Subsystem  
Asynchronous SRAM/ROM/NOR Interface with x8 or x16 data bus  
NAND Interface with x8 data bus  
Muxed/Demuxed OneNAND Interface with x16 data bus  
LPDDR1 Interface with x16 or x32 data bus (266~400Mbps/pin DDR)  
DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR)  
LPDDR2 interface (400Mbps/pin DDR)  
3.1 MICROPROCESSOR  
The ARM CortexTM-A8 processor is the first application processor based on the ARMv7 architecture.  
With the ability to scale in speed from 600MHz to greater than 1GHz, the ARM CortexTM-A8 processor meets  
the requirements for power-optimized mobile devices needing operation in less than 300mW; and  
performance-optimized consumer applications requiring 2000 Dhrystone MIPS.  
ARM's first superscalar processor featuring technology for enhanced code density and performance,  
NEONTM technology for multimedia and signal processing, and Jazelle® RCT technology for efficient support  
of ahead-of-time and just-in-time compilation of Java and other byte code languages.  
ARM CortexTM-A8 Features  
Thumb-2 technology for greater performance, energy efficiency, and code density  
NEONTM signal processing extensions  
Jazelle RCT Java-acceleration technology  
TrustZone technology for secure transactions and DRM  
13-stage main integer pipeline  
10-stage NEONTM media pipeline  
Integrated L2 Cache using standard compiled RAMs  
Optimized L1 caches for performance and power  
1.1-4  
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