S3C80C5 参数 Datasheet PDF下载

型号：	S3C80C5
PDF下载：	下载PDF文件查看货源
内容描述：	8位CMOS微控制器 [8-Bit CMOS Microcontrollers]
分类和应用：	微控制器
文件页数/大小：	263 页 / 1407 K
品牌：	SAMSUNG [ SAMSUNG ]

Table of Contents

Part I — Programming Model

Chapter 1

Product Overview

Overview.................................................................................................................................................1-1

S3P80C5/C80C5/C80C8 Microcontroller .................................................................................................1-1

Features..................................................................................................................................................1-2

CPU ........................................................................................................................................................1-2

Block Diagram.........................................................................................................................................1-3

Pin Assignments......................................................................................................................................1-4

Pin Descriptions.......................................................................................................................................1-5

Pin Circuits..............................................................................................................................................1-6

Chapter 2

Address Spaces

Overview.................................................................................................................................................2-1

Program Memory (ROM) .........................................................................................................................2-2

Register Architecture ...............................................................................................................................2-3

Register Page Pointer (PP) .............................................................................................................2-5

Register Set 1 .................................................................................................................................2-6

Register Set 2 .................................................................................................................................2-6

Prime Register Space .....................................................................................................................2-7

Working Registers...........................................................................................................................2-8

Using The Register Pointers............................................................................................................2-9

Register Addressing.................................................................................................................................2-11

Common Working Register Area (C0H–CFH)..................................................................................2-13

4-Bit Working Register Addressing..................................................................................................2-14

8-Bit Working Register Addressing..................................................................................................2-16

System and User Stacks..........................................................................................................................2-18

Chapter 3

Addressing Modes

Overview.................................................................................................................................................3-1

Register Addressing Mode (R).........................................................................................................3-2

Indirect Register Addressing Mode (IR) ...........................................................................................3-3

Indexed Addressing Mode (X)..........................................................................................................3-7

Direct Address Mode (DA)...............................................................................................................3-10

Indirect Address Mode (IA)..............................................................................................................3-12

Relative Address Mode (RA) ...........................................................................................................3-13

Immediate Mode (IM)......................................................................................................................3-14

S3P80C5/C80C5/C80C8 MICROCONTROLLER

Table of Contents (Continued

Chapter

Control Registers

................................

.................

Chapter 5

Overview ................................

Interrupt Types

................................................................

5-1

5-2

5-3

5-5

Interrupt Structure

Interrupt Vector Addresses

Enable/Disable Interrupt Instructions (EI, DI)

................................................................

...................................................

System-Level Interrupt Control Registers ................................

................................................................

........................5-7

..5-8

5-9

5-10

5-11

5-12

System Mode Register (SYM)

Interrupt Mask Register (IMR)

Interrupt Priority Register (IPR)

Interrupt Request Register (IRQ)

Interrupt Pending Function Types

Interrupt Source Polling Sequence

Interrupt Service Routines

................................................................

................................................................ 5-14

................................................................ 5-15

................................................................ 5-16

................................................................

5-16

Generating Interrupt Vector Addresses

Nesting of Vectored Interrupts ................................

Instruction Pointer (IP)................................

............................................................

.........................................

.....................................................

Fast Interrupt Processing

................................................................

5-17

Chapter

Instruction Set

Overview

................................................................

.................6-1

......................................

........................................................

...........................................................

..................................................

Addressing Modes................................

Flags Register (FLAGS) ................................

Flag Descriptions................................

Instruction Set Notation ................................

Condition Codes................................

.............................................................

...................................................

..............................................................

...................................................

Instruction Descriptions ................................

S3P80C5/C80C5/C80C8 MICROCONTROLLER

Table of Contents (Continued)

Part II Hardware Descriptions

Chapter 7

Clock Circuit

Overview.................................................................................................................................................7-1

System Clock Circuit.......................................................................................................................7-1

Clock Status During Power-Down Modes.........................................................................................7-2

System Clock Control Register (CLKCON)......................................................................................7-3

Chapter 8

RESET and Power-Down

System Reset..........................................................................................................................................8-1

LVD Reset.......................................................................................................................................8-1

Interrupt with Reset (INTR)..............................................................................................................8-2

Watch-Dog Timer Reset..................................................................................................................8-2

Power-on Reset (POR)....................................................................................................................8-2

System Reset Operation .................................................................................................................8-3

Hardware Reset Values...................................................................................................................8-4

Power-Down Modes.................................................................................................................................8-6

Stop mode.......................................................................................................................................8-6

Using POR to Release Stop Mode...................................................................................................8-6

Using an INTR to Release Stop Mode .............................................................................................8-6

Idle Mode........................................................................................................................................8-9

Summary Table of Stop Mode, and Idle Mode.................................................................................8-10

Chapter 9

I/O Ports

Overview.................................................................................................................................................9-1

Port Data Registers.........................................................................................................................9-2

Pull-Up Resistor Enable Registers...................................................................................................9-2

Port 0..............................................................................................................................................9-4

Port 0 Interrupt Enable Register (P0INT).........................................................................................9-5

Port 0 Interrupt Pending Register (P0PND)......................................................................................9-5

Port 1..............................................................................................................................................9-7

Port 2..............................................................................................................................................9-9

Chapter 10

Basic Timer and Timer 0

Module Overview.....................................................................................................................................10-1

Basic Timer Control Register (BTCON) ...............................................................................................10-1

Basic Timer Function Description ........................................................................................................10-3

Timer 0 Control Register (T0CON) ......................................................................................................10-3

Timer 0 Function Description...............................................................................................................10-5

S3P80C5/C80C5/C80C8 MICROCONTROLLER

vii

Table of Contents (Concluded)

Chapter 11

Timer 1

Overview .................................................................................................................................................11-1

Timer 1 Overflow Interrupt...............................................................................................................11-2

Timer 1 Match Interrupt ...................................................................................................................11-2

Timer 1 Control Register (T1CON) ..................................................................................................11-4

Chapter 12

Counter A

Overview .................................................................................................................................................12-1

Counter A Control Register (CACON)..............................................................................................12-3

Counter A Pulse Width Calculations................................................................................................12-4

Chapter 13

Electrical Data

Overview .................................................................................................................................................13-1

Chapter 14

Mechanical Data

Overview .................................................................................................................................................14-1

viii

S3P80C5/C80C5/C80C8 MICROCONTROLLER

List of Figures

Figure

Title

Page

Number

1-1

1-2

1-3

1-4

1-5

1-6

1-7

Block Diagram........................................................................................................1-3

Pin Assignment Diagram (24-Pin SOP/SDIP Package) ..........................................1-4

Pin Circuit Type 1 (Port 0)......................................................................................1-6

Pin Circuit Type 2 (Port 1)......................................................................................1-7

Pin Circuit Type 3 (P2.0) ........................................................................................1-8

Pin Circuit Type 4 (P2.1) ........................................................................................1-9

Pin Circuit Type 5 (P2.2) ........................................................................................1-10

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

Program Memory Address Space...........................................................................2-2

Internal Register File Organization .........................................................................2-4

Set 1, Set 2, and Prime Area Register Map............................................................2-7

8-Byte Working Register Areas (Slices)..................................................................2-8

Contiguous 16-Byte Working Register Block ..........................................................2-9

Non-Contiguous 16-Byte Working Register Block...................................................2-10

16-Bit Register Pair................................................................................................2-11

Common Working Register Area............................................................................2-13

4-Bit Working Register Addressing.........................................................................2-15

4-Bit Working Register Addressing Example ..........................................................2-15

8-Bit Working Register Addressing.........................................................................2-16

8-Bit Working Register Addressing Example ..........................................................2-17

Stack Operations....................................................................................................2-18

2-9

2-10

2-11

2-12

2-13

2-14

2-15

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

Working Register Addressing .................................................................................3-2

Indirect Register Addressing to Register File ..........................................................3-3

Indirect Register Addressing to Program Memory...................................................3-4

Indirect Working Register Addressing to Register File ............................................3-5

Indirect Working Register Addressing to Program or Data Memory ........................3-6

Indexed Addressing to Register File .......................................................................3-7

Indexed Addressing to Program or Data Memory with Short Offset ........................3-8

Indexed Addressing to Program or Data Memory ...................................................3-9

Direct Addressing for Load Instructions ..................................................................3-10

Direct Addressing for Call and Jump Instructions....................................................3-11

Indirect Addressing.................................................................................................3-12

Relative Addressing ...............................................................................................3-13

Immediate Addressing............................................................................................3-14

3-9

3-10

3-11

3-12

3-13

3-14

4-1

S3P80C5/C80C5/C80C8 MICROCONTROLLER

List of Figures (Continued)

Figure

Title

Page

Number

5-1

5-3

5-2

5-4

5-5

5-6

5-7

5-8

5-9

KS88-Series Interrupt Types...................................................................................5-2

ROM Vector Address Area .....................................................................................5-5

Interrupt Structure ..................................................................................................5-4

Interrupt Function Diagram.....................................................................................5-8

System Mode Register (SYM) ................................................................................5-10

Interrupt Mask Register (IMR).................................................................................5-11

Interrupt Request Priority Groups ...........................................................................5-12

Interrupt Priority Register (IPR)...............................................................................5-13

Interrupt Request Register (IRQ) ............................................................................5-14

6-1

System Flags Register (FLAGS).............................................................................6-6

7-1

7-2

7-3

7-4

Main Oscillator Circuit (External Crystal or Ceramic Resonator) .............................7-1

External Clock Circuit.............................................................................................7-1

System Clock Circuit Diagram................................................................................7-2

System Clock Control Register (CLKCON) .............................................................7-3

8-1

8-2

8-3

Reset Block Diagram..............................................................................................8-1

Power-on Reset Circuit...........................................................................................8-2

Timing Diagram for Power-on Reset Circuit............................................................8-3

9-1

9-2

9-3

9-4

9-5

9-6

9-7

9-8

9-9

9-10

S3P80C5/C80C5/C80C8 I/O Port 0 Data Register Format......................................9-2

S3P80C5/C80C5/C80C8 I/O Port 1 Data Register Format......................................9-3

Port 0 High-Byte Control Register (P0CONH).........................................................9-4

Port 0 Low-Byte Control Register (P0CONL) ..........................................................9-5

Port 0 External Interrupt Control Register (P0INT)..................................................9-6

Port 0 External Interrupt Pending Register (P0PND)...............................................9-7

Port 1 High-Byte Control Register (P1CONH).........................................................9-7

Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-8

Port 2 Control Register (P2CON)............................................................................9-9

Port 2 Data Register (P2) .......................................................................................9-10

S3P80C5/C80C5/C80C8 MICROCONTROLLER

List of Figures (Concluded)

Figure

Title

Page

Number

10-1

10-2

10-3

10-4

Basic Timer Control Register (BTCON)..................................................................10-2

Timer 0 Control Register (T0CON).........................................................................10-4

Simplified Timer 0 Function Diagram: Interval Timer Mode....................................10-5

Simplified Timer 0 Function Diagram: PWM Mode.................................................10-6

11-1

11-2

11-3

11-4

Simplified Timer 1 Function Diagram: Interval Timer Mode....................................11-2

Timer 1 Block Diagram...........................................................................................11-3

Timer 1 Control Register (T1CON).........................................................................11-4

Timer 1 Registers...................................................................................................11-5

12-1

12-2

12-3

12-4

Counter A Block Diagram.......................................................................................12-2

Counter A Control Register (CACON).....................................................................12-3

Counter A Registers ...............................................................................................12-4

Counter A Output Flip-Flop Waveforms in Repeat Mode........................................12-5

13-1

13-2

Input Timing for External Interrupts (Port 0)............................................................13-5

Operating Voltage Range ......................................................................................13-6

14-1

14-2

24-Pin SOP Package Mechanical Data ..................................................................14-1

24-Pin SDIP Package Mechanical Data..................................................................14-2

S3P80C5/C80C5/C80C8 MICROCONTROLLER

List of Tables

Table

Title

Page

Number

1-1

2-1

4-1

Pin Descriptions .....................................................................................................1-5

Mapped Registers (Set1)........................................................................................4-2

5-1

5-2

5-3

Interrupt Vectors.....................................................................................................5-6

Interrupt Control Register Overview .......................................................................5-7

Interrupt Source Control and Data Registers...........................................................5-9

6-1

6-2

6-3

6-4

6-5

6-6

Instruction Group Summary....................................................................................6-2

Flag Notation Conventions .....................................................................................6-8

Instruction Set Symbols..........................................................................................6-8

Instruction Notation Conventions............................................................................6-9

Opcode Quick Reference .......................................................................................6-10

Condition Codes.....................................................................................................6-12

8-1

8-2

Set 1 Register Values After Reset ..........................................................................8-4

Summary of Each Mode.........................................................................................8-10

9-1

9-2

S3P80C5/C80C5/C80C8 Port Configuration Overview...........................................9-1

Port Data Register Summary..................................................................................9-2

13-1

13-2

13-3

13-4

13-5

13-6

13-7

13-8

Absolute Maximum Ratings....................................................................................13-2

D.C. Electrical Characteristics................................................................................13-2

Characteristics of Low Voltage Detect circuit..........................................................13-4

Data Retention Supply Voltage in Stop Mode.........................................................13-4

Input/Output Capacitance.......................................................................................13-4

A.C. Electrical Characteristics ................................................................................13-4

Oscillation Characteristics ......................................................................................13-5

Oscillation Stabilization Time .................................................................................13-6

S3P80C5/C80C5/C80C8 MICROCONTROLLER

xiii

List of Programming Tips

Description

Chapter 2:

Page

Number

Address Spaces

Setting the Register Pointers ...............................................................................................................2-9

Using the RPs to Calculate the Sum of a Series of Registers...............................................................2-10

Addressing the Common Working Register Area.................................................................................2-14

Standard Stack Operations Using PUSH and POP..............................................................................2-19

Chapter 8:

RESET and Power-Down

To Divide STOP Mode Releasing and POR.........................................................................................8-8

Chapter 10:

Basic Timer and Timer 0

Configuring the Basic Timer ................................................................................................................10-8

Programming Timer 0..........................................................................................................................10-9

Chapter 12:

Counter A

To Generate 38 kHz, 1/3duty Signal Through P2.1..............................................................................12-6

To Generate a One Pulse Signal Through P2.1...................................................................................12-7

S3P80C5/C80C5/C80C8 MICROCONTROLLER

List of Register Descriptions

Identifier

Full Register Name

Page

Number

BTCON

CACON

Basic Timer Control Register..................................................................................4-5

Counter A Control Register.....................................................................................4-6

CLKCON

EMT

System Clock Control Register...............................................................................4-7

External Memory Timing Register ..........................................................................4-8

System Flags Register ...........................................................................................4-9

Interrupt Mask Register ..........................................................................................4-10

Instruction Pointer (High Byte) ...............................................................................4-11

Instruction Pointer (Low Byte) ................................................................................4-11

Interrupt Priority Register........................................................................................4-12

Interrupt Request Register......................................................................................4-13

Port 0 Control Register (High Byte) ........................................................................4-14

Port 0 Control Register (Low Byte) .........................................................................4-15

Port 0 Interrupt Control Register.............................................................................4-16

FLAGS

IMR

IPH

IPL

IPR

IRQ

P0CONH

P0CONL

P0INT

P0PND

P0PUR

Port 0 Interrupt Pending Register ...........................................................................4-17

Port 0 Pull-up Resistor Enable Register..................................................................4-18

P1CONH

P1CONL

Port 1 Control Register (High Byte) ........................................................................4-19

Port 1 Control Register (Low Byte) .........................................................................4-20

P1PUR

P2CON

Port 1 Pull-up Resistor Enable Register .................................................................4-21

Port 2 Control Register...........................................................................................4-22

Register Pointer 0...................................................................................................4-24

Register Pointer 1...................................................................................................4-24

Stack Pointer (Low Byte)........................................................................................4-25

Stop Control Register.............................................................................................4-25

System Mode Register ...........................................................................................4-26

Timer 0 Control Register ........................................................................................4-27

Timer 1 Control Register ........................................................................................4-28

RP0

RP1

SPL

STOPCON

SYM

T0CON

T1CON

S3P80C5/C80C5/C80C8 MICROCONTROLLER

xvii

List of Instruction Descriptions

Instruction

Mnemonic

Full Register Name

Page

Number

ADC

ADD

AND

BAND

BCP

BITC

BITR

BITS

BOR

BTJRF

BTJRT

BXOR

CALL

CCF

CLR

Add with Carry........................................................................................................6-14

Add ........................................................................................................................6-15

Logical AND...........................................................................................................6-16

Bit AND..................................................................................................................6-17

Bit Compare...........................................................................................................6-18

Bit Complement .....................................................................................................6-19

Bit Reset ................................................................................................................6-20

Bit Set....................................................................................................................6-21

Bit OR....................................................................................................................6-22

Bit Test, Jump Relative on False............................................................................6-23

Bit Test, Jump Relative on True .............................................................................6-24

Bit XOR..................................................................................................................6-25

Call Procedure .......................................................................................................6-26

Complement Carry Flag .........................................................................................6-27

Clear......................................................................................................................6-28

Complement...........................................................................................................6-29

Compare................................................................................................................6-30

Compare, Increment, and Jump on Equal ..............................................................6-31

Compare, Increment, and Jump on Non-Equal.......................................................6-32

Decimal Adjust.......................................................................................................6-33

Decrement .............................................................................................................6-35

Decrement Word....................................................................................................6-36

Disable Interrupts ...................................................................................................6-37

Divide (Unsigned)...................................................................................................6-38

Decrement and Jump if Non-Zero ..........................................................................6-39

Enable Interrupts....................................................................................................6-40

Enter......................................................................................................................6-41

Exit ........................................................................................................................6-42

Idle Operation ........................................................................................................6-43

Increment...............................................................................................................6-44

Increment Word .....................................................................................................6-45

Interrupt Return......................................................................................................6-46

Jump......................................................................................................................6-47

Jump Relative........................................................................................................6-48

Load.......................................................................................................................6-49

Load Bit..................................................................................................................6-51

COM

CPIJE

CPIJNE

DEC

DECW

DIV

DJNZ

ENTER

EXIT

IDLE

INC

INCW

IRET

LDB

S3P80C5/C80C5/C80C8 MICROCONTROLLER

xix

List of Instruction Descriptions (Continued)

Instruction

Mnemonic

Full Register Name

Page

Number

LDC/LDE

LDCD/LDED

LDCI/LDEI

LDCPD/LDEPD

LDCPI/LDEPI

LDW

Load Memory .........................................................................................................6-52

Load Memory and Decrement ................................................................................6-54

Load Memory and Increment..................................................................................6-55

Load Memory with Pre-Decrement .........................................................................6-56

Load Memory with Pre-Increment...........................................................................6-57

Load Word .............................................................................................................6-58

Multiply (Unsigned).................................................................................................6-59

Next .......................................................................................................................6-60

No Operation..........................................................................................................6-61

Logical OR .............................................................................................................6-62

Pop from Stack.......................................................................................................6-63

Pop User Stack (Decrementing) .............................................................................6-64

Pop User Stack (Incrementing)...............................................................................6-65

Push to Stack .........................................................................................................6-66

Push User Stack (Decrementing)............................................................................6-67

Push User Stack (Incrementing) .............................................................................6-68

Reset Carry Flag ....................................................................................................6-69

Return ....................................................................................................................6-70

Rotate Left .............................................................................................................6-71

Rotate Left through Carry .......................................................................................6-72

Rotate Right ...........................................................................................................6-73

Rotate Right through Carry.....................................................................................6-74

Select Bank 0.........................................................................................................6-75

Select Bank 1.........................................................................................................6-76

Subtract with Carry.................................................................................................6-77

Set Carry Flag........................................................................................................6-78

Shift Right Arithmetic..............................................................................................6-79

Set Register Pointer ...............................................................................................6-80

Stop Operation.......................................................................................................6-81

Subtract..................................................................................................................6-82

Swap Nibbles .........................................................................................................6-83

Test Complement under Mask................................................................................6-84

Test under Mask.....................................................................................................6-85

Wait for Interrupt ....................................................................................................6-86

Logical Exclusive OR .............................................................................................6-87

MULT

NOP

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

RCF

RET

RLC

RRC

SB0

SB1

SBC

SCF

SRA

SRP/SRP0/SRP1

STOP

SUB

SWAP

TCM

WFI

XOR

S3P80C5/C80C5/C80C8 MICROCONTROLLER

S3P80C5/C80C5/C80C8

PRODUCT OVERVIEW

OVERVIEW

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range

of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupt

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more

interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to

specific interrupt levels.

S3P80C5/C80C5/C80C8 MICROCONTROLLER

The S3P80C5/C80C5/C80C8 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS

process and is based on Samsung's newest CPU architecture.

The S3C80C5/C80C8 is the microcontroller which has mask-programmable ROM.

The S3P80C5 is the microcontroller which has one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers developed the S3P80C5/C80C5/C80C8 by

integrating the following peripheral modules with the powerful SAM87 RC core:

— Three programmable I/O ports, including two 8-bit ports and one 3-bit port, for a total of 19 pins.

— Internal LVD circuit and eight bit-programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

— One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3P80C5/C80C5/C80C8 is a versatile general-purpose microcontroller which is especially suitable for use

as remote transmitter controller. It is currently available in a 24-pin SOP and SDIP package.

1-1

PRODUCT OVERVIEW

S3P80C5/C80C5/C80C8

FEATURES

CPU

Timers and Timer/Counters

One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer

function

SAM87RC CPU core

Memory

One 8-bit timer/counter (Timer 0) with two

operating modes; Interval mode and PWM mode.

Program memory (ROM)

– S3C80C8: 8-Kbyte

(0000H–1FFFH)

One 16-bit timer/counter with one operating

modes; Interval mode

– S3C80C5: 15,872 byte

(0000H–3E00H)

Low Voltage Detect Circuit

Data memory: 256-byte RAM

Low voltage detect for reset or Back-up mode.

Low level detect voltage

– S3C80C5/C80C8:

1.90 V (Typ) ± 200 mV

Instruction Set

78 instructions

IDLE and STOP instructions added for power-

down modes

Auto Reset Function

Reset occurs when stop mode is released by P0.

Instruction Execution Time

1000 ns at 4-MHz f_OSC(minimum)

When a falling edge is detected at Port 0 during

Stop mode, system reset occurs.

Interrupts

Operating Temperature Range

13 interrupt sources with 10 vector.

5 level, 10 vector interrupt structure

° °

–40 C to + 85 C

•

Operating Voltage Range

1.7 V to 3.6 V at 4 MHz f_OSC

I/O Ports

Two 8-bit I/O ports (P0-P1) and one 3-bit port

(P2) for a total of 19 bit-programmable pins

Package Type

24-pin SOP/SDIP

Eight input pins for external interrupts

Carrier Frequency Generator

One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Back-up mode

When V_DDis lower than V_LVD, the chip enters

Back-up mode to block oscillation and reduce the

current consumption.

1-2

S3P80C5/C80C5/C80C8

PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-P0.7/INT0-INT4

Port 0(INTR)

P1.0-P1.7

Port 1

LVD

TEST

Internal Bus

Main

OSC

XIN

XOUT

P2.0/T0PWM

P2.1/REM

P2.2

Port I/O and Interrupt

Control

Port 2

8-bit

Basic

Timer

SAM87RI CPU

8-bit

Timer/

Counter

Carrier

Generator

(Counter A)

256-Byte

15-Kbyte ROM

16-bit

Timer/

Counter

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW

S3P80C5/C80C5/C80C8

PIN ASSIGNMENTS

VDD

P2.2

VSS

XIN

XOUT

TEST

P2.1/REM/SCLK

P2.0/T0PWN/T0CK/SDAT

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

P0.0/INT0/INTR

P0.1/INT1/INTR

RESET/P0.2/INT2/INTR

P0.3/INT3/INTR

S3C80C5/C80C8

24-SOP/SDIP

(TOP VIEW)

P0.4/INT4/INTR

P0.5/INT4/INTR

P0.6/INT4/INTR

P0.7/INT4/INTR

Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)

1-4

S3P80C5/C80C5/C80C8

PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

Circuit

24-Pin

Shared

Names

Type

Description

Type

Number

Functions

P0.0–P0.7

I/O

I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors are assignable by

software. Pins can be assigned individually

as external interrupt inputs with noise filters,

interrupt enable/ disable, and interrupt

pending control. Interrupt with Reset(INTR)

is assigned to Port 0.

5–12

INT0 – INT4/INTR

P1.0–P1.7

I/O

I/O port with bit-programmable pins.

Configurable to input mode or output mode.

Pin circuits are either push-pull or n-

channel open-drain type. Pull-up resistors

are assignable by software.

13–20

21–23

P2.0

P2.1

P2.2

3-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull

output mode, or n-channel open-drain

output mode. Input mode with pull-up

resistors are assignable by software. The

two pins of port 2 have high current drive

capability.

REM/T0CK

X_IN, X_OUT

TEST

–

System clock input and output pins

–

2, 3

–

Test signal input pin (for factory use only;

must be connected to V_SS).

V_DD

V_SS

–

Power supply input pin

Ground pin

–

1-5

PRODUCT OVERVIEW

S3P80C5/C80C5/C80C8

PIN CIRCUITS

VDD

Pull-up

Resistor

Pull-up

Enable

VDD

Data

Input/Output

Output

Disable

VSS

Noise

filter

External

Interrupt

INTR (Interrupt with RESET)

Stop

Figure 1-3. Pin Circuit Type 1 (Port 0)

NOTE

Interrupt with reset (INTR) is assigned to port 0 of S3P80C5/C80C5/C80C8.

It is designed to release stop status with reset. When the falling/rising edge is detected at any pin of Port

0 during stop status, non vectored interrupt INTR signal occurs, after then system reset occurs

automatically. It is designed for a application which are using “stop mode” like remote controller. If stop

mode is not used, INTR do not operates and it can be discarded.

1-6

S3P80C5/C80C5/C80C8

PRODUCT OVERVIEW

VDD

Pull-up

Resistor

Pull-up

Enable

VDD

Data

Input/Output

Open-drain

Output Disable

VSS

Noise

filter

Normal

Input

Figure 1-4. Pin Circuit Type 2 (Port 1)

VDD

Pull-up Resistor

(Typical 21K

)

Pull-up

Enable

P2CON.0

VDD

Port 2.0 Data

T0_PWN

Data

P2.0/T0PWN

Open-drain

Output

Disable

VSS

P2.0 Input

Figure 1-5. Pin Circuit Type 3 (P2.0)

1-7

PRODUCT OVERVIEW

S3P80C5/C80C5/C80C8

VDD

Pull-up

Resistor

(Typical 21KW)

Pull-up

Enable

P2CON.1

VDD

Port 2.1 Data

Data

CAOF(CACON.0)

Carrier On/Off (P2.5)

P2.1/REM/T0CK

Open-Drain

Output

Disable

VSS

P2.1 Input

T0CK

Noise filter

Figure 1-6. Pin Circuit Type 4 (P2.1)

VDD

Pull-up Resistor

(Typical 21K

)

Pull-up

Enable

VDD

Data

In/Out

Open-drain

Output

Disable

VSS

Normal Input

Figure 1-7. Pin Circuit Type 5 (P2.2)

1-8

S3P80C5/C80C5/C80C8

ADDRESS SPACES

OVERVIEW

The S3P80C5/C80C5/C80C8 microcontroller has two types of address space:

— Internal program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and

data between the CPU and the register file.

The S3C80C5 has an internal 15,872 byte programmable ROM, the S3C80C8 has an internal 8-Kbyte

programmable ROM. An external memory interface is not implemented. The 256-byte physical RAM space is

expanded into an addressable area of 320 bytes by the use of addressing modes.

There are 312 mapped registers in the internal register file. Of these, 272 are for general-purpose use. (This

number includes a 16-byte working register common area that is used as a " scratch area" for data operations, a

256 prime register area that is used for general purpose and stack operation). Eighteen 8-bit registers are used

for CPU and system control and 22 registers are mapped peripheral control and data registers.

2-1

ADDRESS SPACES

S3P80C5/C80C5/C80C8

PROGRAM MEMORY (ROM)

Program memory stores program code or table data. The S3C80C5 has 15, 872 bytes of internal programmable

program memory, and the program memory address range is therefore 0000H-3E00H of ROM. The S3C80C8

has 8-Kbyte (0000H-1FFFH) of internal programmable program memory (see Figure 2-1).

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this

address range can be used as normal program memory. If you do use the vector address area to store program

code, be careful to avoid overwriting vector addresses stored in these locations.

The ROM address at which program execution starts after a reset is 0100H.

(Decimal)

(HEX)

15,872

3E00H

15-Kbyte

ROM

S3C80C5

8,191

1FFFH

S3C80C8

8-Kbyte

ROM

255

0FFH

Interrupt

Vector Area

Figure 2-1. Program Memory Address Space

2-2

S3P80C5/C80C5/C80C8

ADDRESS SPACES

The S3P80C5/C80C5/C80C8 register file has 312 registers. The upper 64 bytes register files are addressed as

system control register and working register. The lower 192-byte area of the physical register file(00H–BFH)

contains freely-addressable, general-purpose registers called prime registers. It can be also used for stack

operation.

The extension of register space into separately addressable sets is supported internally by addressing mode

restrictions.

Specific register types and the area (in bytes) they occupy in the S3P80C5/C80C5/C80C8 internal register space

are summarized in Table 2-1.

Table 2-1. S3P80C5/C80C5/C80C8 Register Type Summary

Number of Bytes

General-purpose registers (including the 16-byte common working register area,

the 256-byte prime register area.)

272

CPU and system control registers

Mapped clock, peripheral, and I/O control and data registers

Total Addressable Bytes

312

2-3

ADDRESS SPACES

S3P80C5/C80C5/C80C8

Set 1

Set 2

FFH

System and Peripheral

Control Registers

(Register Addressing

Mode)

General-Purpose

Data Register

E0H

DFH

(Indirect Register or

Indexed addressing

modes or

64-Bytes

System Registers

(Register Addressing

Mode)

D0H

CFH

stack operations)

Working Registers

(Working Register

Addressing Mode)

C0H

BFH

256-Bytes

192-Bytes

Prime Data Registers

(All Addressing Modes)

00H

Figure 2-2. Internal Register File Organization

2-4

S3P80C5/C80C5/C80C8

ADDRESS SPACES

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using

an 8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by

the register page pointer (PP, DFH). In the S3P80C5/C80C5/C80C8 microcontroller, a paged register file

expansion is not implemented and the register page pointer settings therefore always point to "page 0."

Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always

'0000', automatically selecting page 0 as the source and destination page for register addressing. These page

pointer (PP) register settings, as shown in Figure 2-3, should not be modified during normal operation.

DFH, Set 1, R/W

MSB

LSB

Dectination register page selection bits:

0 0 0 0 Destination: page 0

Source register page selection bits:

0 0 0 0 Source: page 0

NOTE:

In the S3C80C5/C80C8 microcontroller, only pate 0 is implemented.

A hardware reset operation writes the 4-bit destination and source values

shown above to the register pate pointer. These values should not be

modified.

Figure 2-3. Register Page Pointer (PP)

2-5

ADDRESS SPACES

S3P80C5/C80C5/C80C8

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

In some S3C8-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into

two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to

address one bank or the other. In the S3P80C5/C80C5/C80C8 microcontroller, bank 1 is not implemented. A

hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not

necessary.

The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The

lower 32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–

C0H). You can use the common working register area as a "scratch" area for data operations being performed in

other areas of the register file.

Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte

working register area can only be accessed using working register addressing. (For more information about

working register addressing, please refer to Section 3, "Addressing Modes," .)

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another

64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH)

are addressed as part of page 0 in the S3P80C5/C80C5/C80C8 register space.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only

addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-6

S3P80C5/C80C5/C80C8

ADDRESS SPACES

PRIME REGISTER SPACE

The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space

or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other

words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All

registers in prime area locations are addressable immediately following a reset.

Set 1

FFH

FCH

FFH

C0H

Set 2

E0H

D0H

C0H

CPU and system registers

General-purpose registers

Peripheral control registers

Prime

Space

00H

Figure 2-4. Set 1, Set 2 and Prime Area Register Map

2-7

ADDRESS SPACES

S3P80C5/C80C5/C80C8

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as

consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to

form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block

anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected

working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers; R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers; R0–R15)

All of the registers in an 8-byte working register slice have the same binary value for their five most significant

address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.

The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

FFH

Slice 32

F8H

F7H

F0H

Slice 31

1 1 1 1 1 X X X

Set 1

Only

RP1 (Registers R8-R15)

Each register pointer points to

one 8-byte slice of the register

space, selecting a total 16-byte

working register block.

CFH

C0H

0 0 0 0 0 X X X

10H

RP0 (Registers R0-R7)

Slice 2

Slice 1

Figure 2-5. 8-Byte Working Register Areas (Slices)

2-8

S3P80C5/C80C5/C80C8

ADDRESS SPACES

USING THE REGISTER POINTERS

8-byte working register slices in the register file. After a reset, they point to the working register common area:

RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see

Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently

pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in

set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed

addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general

programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see

Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous)

areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can

define the working register area very flexibly to support program requirements.

PROGRAMMING TIP — Setting the Register Pointers

SRP

SRP1

SRP0

CLR

#70H

#48H

#0A0H

RP0

RP1,#0F8H

; RP0 ® 70H, RP1 ® 78H

; RP0 ® no change, RP1 ® 48H,

; RP0 ® A0H, RP1 ® no change

; RP0 ® 00H, RP1 ® no change

; RP0 ® no change, RP1 ® 0F8H

Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

FH (R15)

16-Byte

Contiguous

Working

8-Byte Slice

0 0 0 0 0 X X X

RP0

0H (R0)

Figure 2-6. Contiguous 16-Byte Working Register Block

2-9

ADDRESS SPACES

S3P80C5/C80C5/C80C8

F7H (R7)

F0H (R0)

8-Byte Slice

16-Byte

Contiguous

working

Contains 32

8-Byte Slices

1 1 1 1 0 X X X

RP0

0 0 0 0 0 X X X

RP1

7H (R15)

0H (R0)

8-Byte Slice

Figure 2-7. Non-Contiguous 16-Byte Working Register Block

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H

contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

SRP0

ADD

ADC

#80H

; RP0 ® 80H

R0,R1

R0,R2

R0,R3

R0,R4

R0,R5

; R0 ® R0 + R1

; R0 ® R0 + R2 + C

; R0 ® R0 + R3 + C

; R0 ® R0 + R4 + C

; R0 ® R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this

example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used

to calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

ADC

80H,81H

80H,82H

80H,83H

80H,84H

80H,85H

; 80H ® (80H) + (81H)

; 80H ® (80H) + (82H) + C

; 80H ® (80H) + (83H) + C

; 80H ® (80H) + (84H) + C

; 80H ® (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of

instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.

2-10

S3P80C5/C80C5/C80C8

ADDRESS SPACES

The S3C8-series register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register

pair, you can access all locations in the register file except for set 2. With working register addressing, you use a

space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register

pair, the address of the first 8-bit register is always an even number and the address of the next register is always

an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the

least significant byte is always stored in the next (+ 1) odd-numbered register.

Working register addressing differs from Register addressing because it uses a register pointer to identify a

specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

LSB

n = Even address

Rn+1

Figure 2-8. 16-Bit Register Pair

2-11

ADDRESS SPACES

S3P80C5/C80C5/C80C8

Special-Purpose Registers

General-Purpose Register

Set 1

FFH

Control

Registers

Set 2

System

Registers

D0H

CFH

C0H

BFH

RP1

RP0

D7H

D6H

Pointers

Each register pointer (RP) can independently point

to one of the 24 8-byte "slices" of the register file

(other than set 2). After a reset, RP0 points to

locations C0H-C7H and RP1 to locations C8H-CFH

(that is, to the common working register area).

Prime

Registers

NOTE:

Only page 0 is implemented. Page 0

Contains all of the addressable registers

in the internal register file.

00H

Page 0

All

Indirect

Indexed

Addressing

Modes

Addressing

Modes

Can be Pointed by Register Pointer

Figure 2-9. Register File Addressing

2-12

S3P80C5/C80C5/C80C8

ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations

C0H–CFH, as the active 16-byte working register block:

RP0 ® C0H–C7H

RP1 ® C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working

registers by operations that address any location on any page in the register file. Typically, these working

registers serve as temporary buffers for data operations between different pages.

Page 0

Set 1

FFH

FCH

FFH

E0H

DFH

Set 2

CFH

C0H

BFH

pointers RP0 and RP1 point to the

commom working register area,

locations C0H-CfH.

Prime

Area

RP0 =

RP1 =

1 1 0 0

0 0 0 0

1 0 0 0

00H

Figure 2-10. Common Working Register Area

2-13

ADDRESS SPACES

S3P80C5/C80C5/C80C8

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,

using working register addressing mode only.

Example 1:

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

SRP

#0C0H

R2,40H

; R2 (C2H) ¬ the value in location 40H

Example 2:

ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

SRP

ADD

#0C0H

R3,#45H

; R3 (C3H) ¬ R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in

a register pointer serves as an addressing "window" that makes it possible for instructions to access working

registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected

working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);

— The five high-order bits in the register pointer select an 8-byte slice of the register space;

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are

concatenated with the three low-order bits from the instruction address to form the complete address. As long as

the address stored in the register pointer remains unchanged, the three bits from the address will always point to

an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing: The high-order bit of the instruction

'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the

three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-14

S3P80C5/C80C5/C80C8

ADDRESS SPACES

RP0

RP1

Selects

RP0 or RP1

Address

OPCODE

4-bit Address

Provides Three

Low-order Bits

Provides Five

High-order Bits

Together They Create an

8-bit Register Address

Figure 2-11. 4-Bit Working Register Addressing

RP0

0 1 1 1 0

RP1

0 1 1 1 1

0 0 0

Selects RP0

OPCODE

1 1 1 0

Address

(76H)

Instruction:

'INC R6'

0 1 1 1 0

1 1 0

0 1 1 0

Figure 2-12. 4-Bit Working Register Addressing Example

2-15

ADDRESS SPACES

S3P80C5/C80C5/C80C8

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To

initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit

addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the

three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing: The four high-order bits of the instruction

address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register

address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from

RP1 and the three address bits from the instruction are concatenated to form the complete register address,

0ABH (10101011B).

RP0

RP1

Selects

RP0 or RP1

Address

These Address

Bits Indicate 8-bit

Working Register

Addressing

8-bit Logical

Address

Provides Five

High-order Bits

Three low-

order Bits

8-bit Physical Address

Figure 2-13. 8-Bit Working Register Addressing

2-16

S3P80C5/C80C5/C80C8

ADDRESS SPACES

RP0

0 1 1 0 0

RP1

1 0 1 0 1

0 0 0

Selects RP1

R11

8-bit Address

Form Instruction

'LD R11, R2'

1 1 0 0

0 1 1

Specifies Working

1 0 1 0 1

0 1 1

Figure 2-14. 8-Bit Working Register Addressing Example

2-17

ADDRESS SPACES

S3P80C5/C80C5/C80C8

SYSTEM AND USER STACKS

S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH

and POP instructions are used to control system stack operations.

The S3P80C5/C80C5/C80C8 architecture supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents

of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to

their original locations. The stack address value is always decreased by one before a push operation and

increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top

of the stack, as shown in Figure 2-15.

High Address

PCL

PCH

Top of

PCH

Top of

Stack

FLAGS

Stack Contents

After a Call

Instruction

Stack Contents

After an Interrupt

Low Address

Figure 2-15. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL)

the SPL value is undetermined. Because only internal memory 256-byte is implemented in

S3P80C5/C80C5/C80C8, the SPL must be initialized to an 8-bit value in the range 00H–FFH.

2-18

S3P80C5/C80C5/C80C8

ADDRESS SPACES

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

SPL,#0FFH

; SPL ¬ FFH

; (Normally, the SPL is set to 0FFH by the initialization

; routine)

•

PUSH

•

; Stack address 0FEH ¬ PP

; Stack address 0FDH ¬ RP0

; Stack address 0FCH ¬ RP1

; Stack address 0FBH ¬ R3

RP0

RP1

•

POP

; R3 ¬ Stack address 0FBH

; RP1 ¬ Stack address 0FCH

; RP0 ¬ Stack address 0FDH

; PP ¬ Stack address 0FEH

RP1

RP0

2-19

ADDRESS SPACES

S3P80C5/C80C5/C80C8

NOTES

2-20

S3P80C5/C80C5/C80C8

ADDRESSING MODES

OVERVIEW

The program counter is used to fetch instructions that are stored in program memory for execution. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to

determine the location of the data operand. The operands specified in instructions may be condition codes,

immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are

available for each instruction:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

— Immediate (IM)

3-1

ADDRESSING MODES

S3P80C5/C80C5/C80C8

In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).

Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-

byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory

OPERAND

8-bit Register

File Address

dst

Point to One

File

OPCODE

One-Operand

Instruction

(Example)

Value used in

Instruction Execution

Sample Instruction:

DEC

CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

MSB Points to

RP0 ot RP1

RP0 or RP1

Selected

RP Points

to Start

Program Memory

of Working

Block

4-bit

Working Register

3 LSBs

dst

src

OPERAND

Points to the

Working Register

(1 of 8)

OPCODE

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD R1, R2

;

Where R1 and R2 are registers in the currently

selected working register area.

Figure 3-2. Working Register Addressing

3-2

S3P80C5/C80C5/C80C8

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of

the operand. Depending on the instruction used, the actual address may point to a register in the register file, to

program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to

indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be

accessed using Indirect Register addressing mode.

Program Memory

ADDRESS

8-bit Register

File Address

dst

Point to One

OPCODE

One-Operand

Instruction

(Example)

Address of Operand

used by Instruction

OPERAND

Value used in

Instruction Execution

Sample Instruction:

@SHIFT ; Where SHIFT is the label of an 8-bit register address.

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

S3P80C5/C80C5/C80C8

INDIRECT REGISTER ADDRESSING MODE (Continued)

Program Memory

Example

dst

Instruction

References

Program

Points to

OPCODE

16-Bit

Memory

Address

Points to

Program

Memory

Program Memory

OPERAND

Sample Instructions:

Value used in

Instruction

CALL

@RR2

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

S3P80C5/C80C5/C80C8

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP Points

to Start of

Woking

Block

Program Memory

4-bit

3 LSBs

Working

Address

ADDRESS

dst

src

Point to the

Working Register

(1 of 8)

OPCODE

Sample Instruction:

OR R3, @R6

Value used in

Instruction

OPERAND

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

S3P80C5/C80C5/C80C8

INDIRECT REGISTER ADDRESSING MODE (Continued)

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP Points

to Start of

Working

Block

Program Memory

4-bit Working

dst

src

Pair

Next 2-bit Point

to Working

(1 of 4)

OPCODE

Example Instruction

References either

Program Memory or

Data Memory

16-Bit

Address

Points to

Program

Memory or

Data

Program Memory

Data Memory

LSB Selects

Memory

Value used in

Instruction

OPERAND

Sample Instructions:

LDC

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

NOTE:

LDE command is not available, because an external interface is not implemented for

the S3C80C5/C80C8/C80C4.

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

S3P80C5/C80C5/C80C8

ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to

calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access

locations in the internal register file or in external memory (if implemented). You cannot, however, access

locations C0H–FFH in set 1 using Indexed addressing.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128

to +127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained

in a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for

external data memory (if implemented).

MSB Points to

RP0 or RP1

Selected RP

Points to

Start of

Working

Block

Value used in

Instruction

OPERAND

Program Memory

Base Address

3 LSBs

Two-Operand

Instruction

Example

dst/src

INDEX

Point to One of the

Working Register

(1 of 8)

OPCODE

Sample Instruction:

LD R0, #BASE[R1]

;

Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

S3P80C5/C80C5/C80C8

INDEXED ADDRESSING MODE (Continued)

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP Points

to Start of

Working

Block

Program Memory

OFFSET

Next 2 Bits

4 Bit Working

dst/src

OPCODE

Pair

Point to Working

(1 of 4)

16-Bit

Address

Added to

Offset

LSB Selects

Program Memory

Data Memory

16 Bits

8 Bits

Value used In

Instruction

OPERAND

16 Bits

Sample Instructions:

LDC

LDE

R4, #04H[RR2]

R4,#04H[RR2]

; The values in the program address (RR2 + 04H) are

loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

NOTE:

LDE command is not available, because an external interface is not implemented for

the S3C80C5/C80C8/C80C4.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3P80C5/C80C5/C80C8

ADDRESSING MODES

INDEXED ADDRESSING MODE (Continued)

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP Points

to Start of

Working

Block

Program Memory

OFFSET

Next 2 Bits

4 Bit Working

dst/src

Pair

Point to Working

OPCODE

16 Bit

Address

Added to

Offset

LSB Selects

Program Memory

Data Memory

16-Bits

8-Bits

Value used in

Instruction

OPERAND

16-Bits

Sample Instructions:

LDC

LDE

R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H)

are loaded into register R4.

R4, #1000H[RR2] ; Identical operation to LDC example, except that

external program memory is accessed.

NOTE:

LDE command is not available, because an external interface is not implemented for

the S3C80C5/C80C8/C80C4.

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES

S3P80C5/C80C5/C80C8

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Address

Used

Program Memory

Upper Address Byte

Lower Address Byte

dst/src "0" or "1"

OPCODE

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

Sample Instructions:

LDC

LDE

R5,1234H ; The values in the program address (1234H)

are loaded into register R5.

R5,1234H ; Identical operation to LDC example, except that

external program memory is accessed.

NOTE:

LDE command is not available, because an external interface

is not implemented for the S3C80C5/C80C8/C804C.

Figure 3-10. Direct Addressing for Load Instructions

3-10

S3P80C5/C80C5/C80C8

ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Program Memory

Address Used

Lower Address Byte

Upper Address Byte

OPCODE

Sample Instructions:

C,JOB1

;

Where JOB1 is a 16 bit immediate address

CALL

DISPLAY ; Where DISPLAY is a 16 bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES

S3P80C5/C80C5/C80C8

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program

memory. The selected pair of memory locations contains the actual address of the next instruction to be

executed. Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program

memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are

assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero

dst

Current

OPCODE

Instruction

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H

; The 16 bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

S3P80C5/C80C5/C80C8

ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified

in the instruction. The displacement value is then added to the current PC value. The result is the address of the

next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction

immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The

instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current

PC Value

Displacement

OPCODE

Current Instruction

Signed Displacement

Value

Sample Instructions:

ULT,$+OFFSET

;

Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES

S3P80C5/C80C5/C80C8

IMMEDIATE MODE (IM)

In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.

The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing

mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3P80C5/C80C5/C80C8 control registers are presented in an easy-to-

read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1

illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed

information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual.

Data and counter registers are not described in detail in this reference section. More information about all of the

registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this

manual.

4-1

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

Table 4-1. Mapped Registers (Set 1)

Mnemonic

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

Decimal

208

Hex

R/W

R^(note)

R/W

Timer 0 counter

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

209

210

211

212

213

214

RP1

215

Locations D8H is not mapped.

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Port 0 data register

SPL

IPH

IPL

IRQ

IMR

SYM

217

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

R/W

R ^(note)

R/W

218

219

220

221

222

223

224

225

226

Port 1 data register

Port 2 data register

Location E3H–E6H is not mapped.

Port 0 pull-up resistor enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 1 pull-up resistor enable register

P0PUR

P0CONH

P0CONL

P1CONH

P1CONL

P1PUR

231

E7H

E8H

E9H

EAH

EBH

ECH

R/W

232

233

234

235

236

Location EDH–EFH is not mapped.

Port 2 control register

P2CON

P0INT

239

241

242

243

244

245

246

247

248

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

R/W

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

P0PND

R/W

CACON

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

R/W

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

R/W

R ^(note)

R/W

4-2

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

Table 4-1. Mapped Registers (Continued)

Mnemonic

T1DATAL

T1CON

Decimal

249

Hex

R/W

Timer 1 data register (low byte)

Timer 1 control register

STOP Control register

F9H

FAH

FBH

250

STOPCON

251

Locations FCH is not mapped.

R ^(note)

R/W

Basic timer counter

BTCNT

EMT

253

FDH

FEH

FFH

External memory timing register

Interrupt priority register

254

255

IPR

R/W

NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.

4-3

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

Bit number(s) that is/are appended to

the register name for bit addressing

Name of individual

bit or related bits

in the internal

(hexadecimal)

FLAGS- System Flags Register

D5H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Bit Addressing Mode Register addressing mode only

Carry Flag (C)

Operation does not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit 7

Zero Flag (Z)

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

'-' = Not used

Description of the

effect of specific

bit settings

Bit number:

MSB = Bit 7

LSB = Bit 0

Addressing mode or

modes you can use

to modify register

values

RESET value notation:

'-' = Not used

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

Figure 4-1. Register Description Format

4-4

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

BTCON — Basic Timer Control Register

D3H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Bit Addressing

.7–.4

.3–.2

Watchdog Timer Function Disable Code (for System Reset)

Disable watchdog timer function

Enable watchdog timer function

Any other value

Basic Timer Input Clock Selection Bits

f_OSC/4096

f_OSC/1024

f_OSC/128

Invalid setting; not used for S3P80C5/C80C5/C80C8.

Basic Timer Counter Clear Bit ⁽¹⁾

No effect

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 ⁽²⁾

No effect

Clear both clock frequency dividers

NOTES:

1. When you write a "1" to BTCON.1, the basic timer counter value is cleared to '00H'. Immediately following the write

operation, the BTCON.1 value is automatically cleared to "0".

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the

write operation, the BTCON.0 value is automatically cleared to "0".

4-5

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

CACON— Counter A Control Register

F3H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

Counter A Input Clock Selection Bits

f_OSC

f_OSC/2

f_OSC/4

f_OSC/8

.5–.4

Counter A Interrupt Timing Selection Bits

Elapsed time for Low data value

Elapsed time for High data value

Elapsed time for combined Low and High data values

Invalid setting; not used for S3C80C5/C80C8.

Counter A Interrupt Enable Bit

Disable interrupt

Enable interrupt

Counter A Start Bit

Stop counter A

Start counter A

Counter A Mode Selection Bit

One-shot mode

Repeating mode

Counter A Output flip-flop Control Bit

Flip-flop Low level (T-FF = Low)

Flip-flop High level (T-FF = High)

4-6

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

CLKCON— System Clock Control Register

D4H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

.6–.5

.4–.3

Oscillator IRQ Wake-up Function Enable Bit

Not used for S3P80C5/C80C5/C80C8.

Main Oscillator Stop Control Bits

Not used for S3P80C5/C80C5/C80C8.

CPU Clock (System Clock) Selection Bits ⁽¹⁾

f_OSC/16

f_OSC/8

f_OSC/2

f_OSC(non-divided)

Subsystem Clock Selection Bit ⁽²⁾

.2–.0

Invalid setting for S3P80C5/C80C5/C80C8.

Select main system clock (MCLK)

Other value

NOTES:

1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the

appropriate values to CLKCON.3 and CLKCON.4.

2. These selection bits are required only for systems that have a main clock and a subsystem clock. The

S3P80C5/C80C5/C80C8 uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.

4-7

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

EMT— External Memory Timing Register ^(note)

FEH

Set 1

Bit Identifier

–

RESET Value

Read/Write

R/W

–

Addressing Mode

External WAIT Input Function Enable Bit

Disable WAIT input function for external device

Enable WAIT input function for external device

Slow Memory Timing Enable Bit

Disable WAIT input function for external device

Enable WAIT input function for external device

.5–.4

Program Memory Automatic Wait Control Bits

No wait

Wait one cycle

Wait two cycles

Wait three cycles

.3–.2

Data Memory Automatic Wait Control Bits

No wait

Wait one cycle

Wait two cycles

Wait three cycles

Stack Area Selection Bit

Select internal register file area

Select external data memory area

Not used for S3P80C5/C80C5/C80C8.

NOTE: The EMT register is not used for S3P80C5/C80C5/C80C8, because an external peripheral interface is not

implemented in the S3P80C5/C80C5/C80C8.

The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT

values during normal operation may cause a system malfunction.

4-8

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

FLAGS — System Flags Register

D5H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

Carry Flag (C)

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

Operation result is £ +127 or ³ –128

Operation result is > +127 or < –128

Decimal Adjust Flag (D)

Add operation completed

Subtraction operation completed

Half-Carry Flag (H)

No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

Interrupt return (IRET) in progress (when read)

Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

Bank 0 is selected

(normal setting for S3C80C5/C80C8)

Invalid selection (bank 1 is not implemented)

4-9

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

IMR— Interrupt Mask Register

DDH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4

Enable (un-mask)

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0

Disable (mask)

Enable (un-mask)

Not used for S3P80C5/C80C5/C80C8.

Interrupt Level 4 (IRQ4) Enable Bit; Counter A Interrupt

Disable (mask)

Enable (un-mask)

.3–.2

Not used for S3P80C5/C80C5/C80C8.

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow

Disable (mask)

Enable (un-mask)

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow

Disable (mask)

Enable (un-mask)

NOTES:

1. When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

2. Interrupt levels IRQ2, IRQ3 and IRQ5 are not used in the S3P80C5/C80C5/C80C8 interrupt structure.

4-10

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

IPH— Instruction Pointer (High Byte)

DAH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.0

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction

pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL

IPL— Instruction Pointer (Low Byte)

DBH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.0

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH

4-11

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

IPR— Interrupt Priority Register

FFH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Bit Addressing

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C

Group priority undefined

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

Group priority undefined

Interrupt Subgroup C Priority Control Bit

IRQ6 > IRQ7

IRQ7 > IRQ6

.5, .3

Not used for S3P80C5/C80C5/C80C8.

Input Group B Priority Control Bit

IRQ4

Interrupt Group A Priority Control Bit

IRQ0 > IRQ1

IRQ1 > IRQ0

NOTE: The S3P80C5/C80C5/C80C8 interrupt structure uses only five levels:

IRQ0, IRQ1, IRQ4, IRQ6–IRQ7. Because IRQ2, IRQ3, IRQ5 are not recognized, the interrupt subgroup B and

group C settings (IPR.2,.3 and IPR.5) are not evaluated.

4-12

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

IRQ— Interrupt Request Register

DCH

Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4

Not pending

Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0

Not pending

Pending

Not used for S3P80C5/C80C5/C80C8.

Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt

Not pending

Pending

.3–.2

Not used for S3P80C5/C80C5/C80C8.

Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow

Not pending

Pending

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow

Not pending

Pending

NOTE: Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3P80C5/C80C5/C80C8 interrupt structure.

4-13

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

P0CONH— Port 0 Control Register (High Byte)

E8H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

.5–.4

.3–.2

P0.7/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.6/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.5/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1–.0

P0.4/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:

1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector

address (E8H).

2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

4-14

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

P0CONL— Port 0 Control Register (Low Byte)

E9H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

.5–.4

.3–.2

P0.3/INT3 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.2/INT2 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.1/INT1 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1–.0

P0.0/INT0 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:

1. The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector

address.

2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

4-15

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

P0INT— Port 0 External Interrupt Enable Register

F1H

Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

P0.7 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.6 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.5 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.4 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.3 External Interrupt (INT3) Enable Bit

Disable interrupt

Enable interrupt

P0.2 External Interrupt (INT2) Enable Bit

Disable interrupt

Enable interrupt

P0.1 External Interrupt (INT1) Enable Bit

Disable interrupt

Enable interrupt

P0.0 External Interrupt (INT0) Enable Bit

Disable interrupt

Enable interrupt

4-16

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

P0PND— Port 0 External Interrupt Pending Register

F2H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

P0.7 External Interrupt (INT4) Pending Flag ^(note)

No P0.7 external interrupt pending (when read)

P0.7 external interrupt is pending (when read)

P0.6 External Interrupt (INT4) Pending Flag

No P0.6 external interrupt pending (when read)

P0.6 external interrupt is pending (when read)

P0.5 External Interrupt (INT4) Pending Flag

No P0.5 external interrupt pending (when read)

P0.5 external interrupt is pending (when read)

P0.4 External Interrupt (INT4) Pending Flag

No P0.4 external interrupt pending (when read)

P0.4 external interrupt is pending (when read)

P0.3 External Interrupt (INT3) Pending Flag

No P0.3 external interrupt pending (when read)

P0.3 external interrupt is pending (when read)

P0.2 External Interrupt (INT2) Pending Flag

No P0.2 external interrupt pending (when read)

P0.2 external interrupt is pending (when read)

P0.1 External Interrupt (INT1) Pending Flag

No P0.1 external interrupt pending (when read)

P0.1 external interrupt is pending (when read)

P0.0 External Interrupt (INT0) Pending Flag

No P0.0 external interrupt pending (when read)

P0.0 external interrupt is pending (when read)

NOTE: To clear an interrupt pending condition, write a "0" to the appropriate pending flag. Writing a "1" to an interrupt

pending flag (POND.0–7) has no effect.

4-17

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

P0PUR— Port 0 Pull-up Resistor Enable Register

E7H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

P0.7 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.6 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.5 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.4 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.3 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.2 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.1 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.0 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

4-18

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

P1CONH— Port 1 Control Register (High Byte)

EAH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

.5–.4

.3–.2

.1–.0

P1.7 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

P1.6 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

P1.5 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

P1.4 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

4-19

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

P1CONL— Port 1 Control Register (Low Byte)

EBH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

.5–.4

.3–.2

.1–.0

P1.3 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

P1.2 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

P1.1 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

P1.0 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid setting

4-20

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

P1PUR— Port 0 Pull-up Resistor Enable Register

ECH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

P1.7 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.6 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.5 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.4 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.3 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.2 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.1 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.0 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

4-21

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

P2CON— Port 2 Control Register

F0H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

.5–.4

.3–.2

P2.2 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P2.1 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P2.0 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P2.1 Alternative Function Selection Bits

Normal I/O function

REM/T0CK function

P2.0 Alternative Function Selection Bits

Normal I/O function

T0PWN function

4-22

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

PP— Register Page Pointer

DFH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.4

Destination Register Page Selection Bits

Destination: page 0 ^(note)

.3–.0

Source Register Page Selection Bits Bits

Source: page 0 ^(note)

NOTE: In the S3P80C5/C80C5/C80C8 microcontroller, a paged expansion of the

internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values

for the source and destination register page are automatically set to '0000B' following a hardware reset. These

values should not be changed during normal operation.

4-23

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

RP0— Register Pointer 0

D6H

Set 1

Bit Identifier

–

RESET Value

Read/Write

R/W

–

Addressing Mode

.7–.3

.2–.0

Destination Register Page Selection Bits

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to address C0H in register set 1, selecting the 8-byte working register

slice C0H–C7H.

Not used for S3P80C5/C80C5/C80C8.

RP1— Register Pointer 1

D7H

Set 1

Bit Identifier

–

RESET Value

Read/Write

R/W

–

Addressing Mode

.7–.3

.2–.0

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to address C8H in register set 1, selecting the 8-byte working register

slice C8H–CFH.

Not used for S3P80C5/C80C5/C80C8.

4-24

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

SPL— Stack Pointer (Low Byte)

D9H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.0

Stack Pointer Address (Low Byte)

The SP value is undefined following a reset.

STOPCON— Stop Control Register

FBH

Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.0

Stop Control Register enable bits

Enable STOPCON

NOTES:

1. To get into STOP mode, stop control register must be enabled just before STOP instruction.

2. When STOP mode is released, stop control register (STOPCON) value is cleared automatically.

3. It is prohibited to write another value into STOPCON.

4-25

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

SYM— System Mode Register

DEH

Set 1

Bit Identifier

–

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Tri-State External Interface Control Bit ⁽¹⁾

Normal operation (disable tri-state operation)

Set external interface lines to high impedance (enable tri-state operation)

.6–.5

.4–.2

Not used for S3P80C5/C80C5/C80C8.

Fast Interrupt Level Selection Bits ⁽²⁾

IRQ0

IRQ1

Not used for

S3P80C5/C80C5/C80C8.

IRQ6

IRQ7

Fast Interrupt Enable Bit ⁽³⁾

Disable fast interrupt processing

Enable fast interrupt processing

Global Interrupt Enable Bit ⁽⁴⁾

Disable global interrupt processing

Enable global interrupt processing

NOTES:

1. Because an external interface is not implemented for the S3P80C5/C80C5/C80C8, SYM.7 must always be "0".

2. You can select only one interrupt level at a time for fast interrupt processing.

3. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.

4. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"

to SYM.0).

4-26

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

T0CON— Timer 0 Control Register

D2H

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

Timer 0 Input Clock Selection Bits

f_OSC/4096

f_OSC/256

f_OSC/8

External clock input (at the T0CK pin, P2.1)

.5–.4

Timer 0 Operating Mode Selection Bits

Interval timer mode (counter cleared by match signal)

Overflow mode (OVF interrupt can occur)

PWM mode (OVF interrupt can occur)

Timer 0 Counter Clear Bit

No effect (when write)

Clear T0 counter, T0CNT (when write)

Timer 0 Overflow Interrupt Enable Bit ^(note)

Disable T0 overflow interrupt

Enable T0 overflow interrupt

Timer 0 Match Interrupt Enable Bit

Disable T0 match interrupt

Enable T0 match interrupt

Timer 0 Match Interrupt Pending Flag

No T0 match interrupt pending (when read)

Clear T0 match interrupt pending condition (when write)

T0 match interrupt is pending (when read)

No effect (when write)

NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0

match/ capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.

4-27

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

T1CON— Timer 1 Control Register

FAH

Set 1

Bit Identifier

RESET Value

Read/Write

R/W

Addressing Mode

.7–.6

Timer 1 Input Clock Selection Bits

f_OSC/4

f_OSC/8

f_OSC/16

Internal clock (counter a flip-flop, T-FF)

.5–.4

Timer 1 Operating Mode Selection Bits

Interval timer mode (counter cleared by match signal)

Overflow mode (OVF interrupt can occur)

Timer 1 Counter Clear Bit

No effect (when write)

Clear T1 counter, T1CNT (when write)

Timer 1 Overflow Interrupt Enable Bit ^(note)

Disable T1 overflow interrupt

Enable T1 overflow interrupt

Timer 1 Match/Capture Interrupt Enable Bit

Disable T1 match interrupt

Enable T1 match interrupt

Timer 1 Match/Capture Interrupt Pending Flag

No T1 match interrupt pending (when read)

Clear T1 match interrupt pending condition (when write)

T1 match interrupt is pending (when read)

No effect (when write)

NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/

capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.

4-28

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

OVERVIEW

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM87 CPU

recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level

has more than one vector address, the vector priorities are established in hardware. A vector address can be

assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks

can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight

possible interrupt levels: IRQ0–IRQ7, also called level 0 – level 7. Each interrupt level directly corresponds to an

interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from

device to device. The S3P80C5/C80C5/C80C8 interrupt structure recognizes five interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are

simply identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt

levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled

by IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.

The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors

used for S3C8-series devices is always much smaller.) If an interrupt level has more than one vector address, the

vector priorities are set in hardware. The S3P80C5/C80C5/C80C8 uses ten vectors. One vector address is

shared by four interrupt sources.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for

example. Each vector can have several interrupt sources. In the S3P80C5/C80C5/C80C8 interrupt structure,

there are thirteen possible interrupt sources.

When a service routine starts, the respective pending bit is either cleared automatically by hardware or is must

be cleared "manually" by program software. The characteristics of the source's pending mechanism determine

which method is used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE

INTERRUPT TYPES

S3P80C5/C80C5/C80C8

The three components of the S3C8 interrupt structure described above — levels, vectors, and sources — are

combined to determine the interrupt structure of an individual device and to make full use of its available

interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,

2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1:

Type 2:

Type 3:

One level (IRQn) + one vector (V ) + one source (S )

1 1

One level (IRQn) + one vector (V ) + multiple sources (S – S )

One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S , S

n+1

– S )

n+m

In the S3P80C5/C80C5/C80C8 microcontroller, all three interrupt types are implemented.

Levels

Vectors

Sources

Type 1:

Type 2:

IRQn

Type 3:

Sn + 1

Sn + 2

Sn + m

NOTES:

1. The number of Sn and Vn value is expandable.

2. In the S3P80C5/C80C5/C80C8 implementation, interrupt types 1, 2, and 3 is used.

Figure 5-1. S3C8-Series Interrupt Types

5-2

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE

The S3P80C5 microcontroller supports two kinds interrupt structure

— Vectored Interrupt

— Non vectored interrupt (Reset interrupt): INTR

The S3P80C5/C80C5/C80C8 microcontroller supports thirteen interrupt sources. Nine of the interrupt sources

have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector

address. Five interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in

Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which

contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt

with the lowest vector address is usually processed first. (The relative priorities of multiple interrupts within a

single level are fixed in hardware.)

When the CPU grants an interrupt request, interrupt processing starts: All other interrupts are disabled and the

program counter value and state flags are pushed to stack. The starting address of the service routine is fetched

from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the

service routine is executed. The S3P80C5/C80C5/C80C8 microcontroller supports non vectored interrupt -

Interrupt with Reset(INTR) - to occur interrupt with system reset. The Interrupt with Reset(INTR) has nothing to do

with interrupt levels, vectors and the registers that are related to interrupt setting. It occurs only according to the

“P0” during “ STOP ” regardless any other things. Namely, only when a falling/rising edge occurs at any pin of

Port 0 during STOP status, this INTR and a system reset occurs even though SYM.0 is “0”(Disable interrupt). But

it dose not occurs while the oscillation - “IDLE” or “OPERATING” status- even though a falling/rising edge occurs

at port 0.

Following is the sequence that occurs Interrupt with Reset(INTR).

1. The oscillation status is “freeze” : STOP mode

2. A falling/rising edge is detected to any pin of Port 0.

3. INTR occurs and it makes system reset.

4. STOP mode is released by this system reset.

NOTE

Because H/W reset occurs whenever INTR occurs. A user should aware of the each ports, system

5-3

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

Levels

Vectors

Sources

Reset/Clear

H/W

S/W

H/W

S/W

H/W

S/W

RESET

100H

FCH

FAH

F6H

F4H

ECH

E6H

E4H

E2H

E0H

Basic timer overflow/INTR/POR

Timer 0 match

IRQ0

Timer 0 overflow

Timer 1 match

IRQ1

IRQ4

Timer 1 overflow

Counter A

P0.3 external interrupt

P0.2 external interrupt

P0.1 external interrupt

P0.0 external interrupt

P0.7 external interrupt

P0.6 external interrupt

P0.5 external interrupt

P0.4 external interrupt

IRQ6

IRQ7

E8H

NOTE:

For interrupt levels with two or more vectors, the lowest vector address

usually the highest priority. For example, FAH has the higher priority (0)

than FCH (1) within level IRQ0. These priorities are fixed in hardware.

Figure 5-2. S3P80C5/C80C5/C80C8 Interrupt Structure

5-4

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

INTERRUPT VECTOR ADDRESSES

All interrupt vector addresses for the S3P80C5/C80C5/C80C8 interrupt structure are stored in the vector address

area of the internal program memory ROM, 00H–FFH. You can allocate unused locations in the vector address

area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector

addresses. (Table 5-2 lists all vector addresses.)

The program reset address in the ROM is 0100H.

(Decimal)

(HEX)

15,872

3E00H

15-Kbyte

ROM

S3C80C5

8,191

1FFFH

S3C80C8

8-Kbyte

ROM

255

0FFH

Interrupt

Vector Area

Figure 5-3. ROM Vector Address Area

5-5

INTERRUPT STRUCTURE

Vector Address

S3P80C5/C80C5/C80C8

Reset/Clear

Table 5-1. S3P80C5/C80C5/C80C8 Interrupt Vectors

Interrupt Source

Request

Decimal

Value

Hex

Value

Interrupt

Level

Priority in

Level

H/W

S/W

100H

254

Basic timer overflow

–

RESET

252

250

246

244

236

232

230

228

226

224

FCH

FAH

F6H

F4H

ECH

E8H

E6H

E4H

E2H

E0H

Timer 0 (match)

IRQ0

–

Timer 0 overflow

Timer 1 (match)

IRQ1

Timer 1 overflow

Counter A

IRQ4

IRQ7

P0.7 external interrupt

P0.6 external interrupt

P0.5 external interrupt

P0.4 external interrupt

P0.3 external interrupt

P0.2 external interrupt

P0.1 external interrupt

P0.0 external interrupt

IRQ6

NOTES:

1. Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on.

2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority

over one with a higher vector address. The priorities within a given level are fixed in hardware.

5-6

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then

serviced as they occur, and according to the established priorities.

NOTE

The system initialization routine that is executed following a reset must always contain an EI instruction

to globally enable the interrupt structure.

During normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable

interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can

manipulate SYM.0 directly to enable or disable interrupts, we recommend that you use the EI and DI instructions

instead.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt

processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to

each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable

fast interrupts and control the activity of external interface, if implemented).

Table 5-2. Interrupt Control Register Overview

Control Register

R/W

Function Description

Interrupt mask register

IMR

R/W

Bit settings in the IMR register enable or disable interrupt

processing for each of the five interrupt levels: IRQ0, IRQ1,

IRQ4, and IRQ6–IRQ7.

Interrupt priority register

IPR

R/W

Controls the relative processing priorities of the interrupt

levels. The five levels of the S3P80C5/C80C5/C80C8 are

organized into three groups: A, B, and C. Group A is IRQ0 and

IRQ1, group B is IRQ4, and group C is IRQ6, and IRQ7.

Interrupt request register

System mode register

IRQ

This register contains a request pending bit for each interrupt

level.

SYM

R/W

Dynamic global interrupt processing enable/ disable, fast

interrupt processing, and external interface control (An

external memory interface is not implemented in the

S3P80C5/C80C5/C80C8 microcontroller).

5-7

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.

The system-level control points in the interrupt structure are, therefore:

— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing the part of your application program that handles interrupt processing, be sure to include

the necessary register file address (register pointer) information.

Interrupt Request

Polling

Cycle

RESET

IRQ0, IRQ1,

IRQ4 and IRQ6- IRQ7

Interrupts

Interrupt Priority

Vector

Interrupt

Cycle

Interrupt Mask

Global Interrupt Control

(EI, DI, or SYM.0

manipulation)

Figure 5-4. Interrupt Function Diagram

5-8

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the

interrupt generated by that peripheral (see Table 5-3).

Table 5-3. Interrupt Source Control and Data Registers

Interrupt Source

Interrupt Level

T0CON ^(note)

Location(s) in Set 1

D2H

D1H

Timer 0 match or timer 0

overflow

IRQ0

IRQ1

IRQ4

IRQ7

T0DATA

T1CON ^(note)

T1DATAH, T1DATAL

Timer 1 match or timer 1

overflow

FAH

F8H, F9H

Counter A

CACON

CADATAH, CADATAL

F3H

F4H, F5H

P0.7 external interrupt

P0.6 external interrupt

P0.5 external interrupt

P0.4 external interrupt

P0CONH

P0INT

P0PND

E8H

F1H

F2H

P0.3 external interrupt

P0.2 external interrupt

P0.1 external interrupt

P0.0 external interrupt

IRQ6

P0CONL

P0INT

P0PND

E9H

F1H

F2H

NOTE: Because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the T0CON and T1CON registers

control only the enable/disable functions. The T0CON and T1CON registers contain enable/disable and pending

bits for the timer 0 and timer 1 match interrupts, respectively.

5-9

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to

control fast interrupt processing (see Figure 5-5).

A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2,

is undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0

value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which

follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to

enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this

purpose.

System Mode Register (SYM)

DEH, Set 1, R/W

MSB

LSB

External interface

tri-state enable bit:

0 = Normal (Tri-state)

1 = High (Tri-state)

Global interrupt enable bit:

0 = Disable all interrupts

1 = Enable all interrupts

Fast interrupt enable bit:

0 = Disable fast interrupt

1 = Enable fast interrupt

Fast interrupt level

selection bits:

Not used for the S3C80C5/C80C8.

0 0 0 IRQ0

0 0 1 IRQ1

0 1 0 Not used

0 1 1 Not used

1 0 0 Not used

1 0 1 Not used

1 1 0 IRQ6

1 1 1 IRQ7

NOTE:

An external memory interface is not implemented.

Figure 5-5. System Mode Register (SYM)

5-10

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual

interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required

settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit

of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a

level's IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions

using the Register addressing mode.

Interrupt Mask Register (IMR)

DDH, Set 1, R/W

MSB

LSB

IRQ7

IRQ0

IRQ6

IRQ1

Not used

IRQ4

Interrupt level enable bits (7-6, 4, 1, 0):

0 = Disable (mask) interrupt

1 = Enable (un-mask) interrupt

Figure 5-6. Interrupt Mask Register (IMR)

5-11

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels

used in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must

therefore be written to their required settings by the initialization routine.

When more than one interrupt source is active, the source with the highest priority level is serviced first. If both

sources belong to the same interrupt level, the source with the lowest vector address usually has priority (This

priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by

the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register

priority definitions (see Figure 5-7):

Group A

Group B

Group C

IRQ0, IRQ1

IRQ4

IRQ6, IRQ7

IPR

Group A

Group B

Group C

IRQ0

IRQ1

IRQ4

IRQ6

IRQ7

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.

For example, the setting '001B' for these bits would select the group relationship B > C > A; the setting '101B'

would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of group C interrupts.

— Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2,

3, and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. In the

S3P80C5/C80C5/C80C8 implementation, interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3

settings are not evaluated, as IRQ4 is the only remaining level in the group.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-12

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

Interrupt Priority Register (IPR)

FFH, Set 1, Bank 0, R/W

MSB

LSB

Group priority:

D7 D4 D1

Group A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

Group B^(note)

0 = IRQ4

0 = Undefined

1 = B > C > A

0 = A > B > C

1 = B > A > C

0 = C > A > B

1 = C > B > A

0 = A > C > B

1 = Undefined

1 = IRQ4

Subgroup B^(note)

0 = IRQ4

1 = IRQ4

Group C^(note)

0 = IRQ6, IRQ7

1 = IRQ6, IRQ7

Subgroup C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

NOTE: In this device interrupt structure, only levels IRQ0, IRQ1, IRQ4, IRQ6-IRQ7

are used. Settings for group/subgroup B, which control relative priorities for

levels IRQ2, IRQ3 and IRQ5, are therefore not evaluated.

Figure 5-8. Interrupt Priority Register (IPR)

5-13

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for

all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same

number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued

for that level; a "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of

the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of

specific interrupt levels. After a reset, all IRQ status bits are cleared to "0".

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing

is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,

however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events

occurred while the interrupt structure was globally disabled.

Interrupt Request Register (IRQ)

DCH, Set 1, Read-only

MSB

LSB

IRQ0

IRQ1

Not

used

Not

used

IRQ4

Not

IRQ6

used

IRQ7

Interrupt level request pending bits:

0 = Interrupt level is not pending

1 = Interrupt level is pending

Figure 5-9. Interrupt Request Register (IRQ)

5-14

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt

service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding

pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is

waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service

routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or

written by application software.

In the S3P80C5/C80C5/C80C8 interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1),

and the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared

automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit must be cleared by program software. The service routine must clear the

appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written

to the corresponding pending bit location in the source's mode or control register.

In the S3P80C5/C80C5/C80C8 interrupt structure, pending conditions for all interrupt sources except the timer 0

and timer 1 overflow interrupts and the counter A borrow interrupt, must be cleared by the interrupt service

routine.

5-15

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the source's interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request can be serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one level is currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.

The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores

the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request.

5-16

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that

correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,

you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it

occurs).

4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the

previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the above procedure to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is used by all S3C8-series microcontrollers to control the optional high-speed interrupt

processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The IP register names

are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in

approximately six clock cycles instead of the usual 16 clock cycles. To select a specific interrupt level for fast

interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt

processing for the selected level, you set SYM.1 to "1".

5-17

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the

program counter values), and

— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated

NOTE

For the S3P80C5/C80C5/C80C8 microcontroller, the service routine for any one of the five interrupt

levels: IRQ0, IRQ1, IRQ4 or IRQ6–IRQ7, can be selected for fast interrupt processing.

Procedure for Initiating Fast Interrupts

To initiate fast interrupt processing, follow these steps:

1. Load the start address of the service routine into the instruction pointer (IP).

2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)

3. Write a "1" to the fast interrupt enable bit in the SYM register.

Fast Interrupt Service Routine

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

1. The contents of the instruction pointer and the PC are swapped.

2. The FLAG register values are written to the FLAGS' ("FLAGS prime") register.

3. The fast interrupt status bit in the FLAGS register is set.

4. The interrupt is serviced.

5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction

pointer and PC values are swapped back.

6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.

7. The fast interrupt status bit in FLAGS is cleared automatically.

Relationship to Interrupt Pending Bit Types

As described previously, there are two types of interrupt pending bits: One type is automatically cleared by

hardware after the interrupt service routine is acknowledged and executed, and the other type must be cleared by

the application program's interrupt service routine. You can select fast interrupt processing for interrupts with

either type of pending condition clear function — by hardware or by software.

Programming Guidelines

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the

SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,

including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast

interrupt service routine ends.

5-18

S3P80C5/C80C5/C80C8

INSTRUCTION SET

OVERVIEW

The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8

microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the

instruction set include:

— A full complement of 8-bit arithmetic and logic operations, including multiply and divide

— No special I/O instructions (I/O control/data registers are mapped directly into the register file)

— Decimal adjustment included in binary-coded decimal (BCD) operations

— 16-bit (word) data can be incremented and decremented

— Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES

The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can

be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least

significant (right-most) bit.

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is

specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory

addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."

ADDRESSING MODES

There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA),

Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please

refer to Section 3, "Addressing Modes."

6-1

INSTRUCTION SET

S3P80C5/C80C5/C80C8

Table 6-1. Instruction Group Summary

Operands Instruction

Mnemonic

Load Instructions

CLR

dst

Clear

dst, src

dst

Load

LDB

Load bit

LDE

Load external data memory

Load program memory

LDC

LDED

LDCD

LDEI

Load external data memory and decrement

Load program memory and decrement

Load external data memory and increment

Load program memory and increment

Load external data memory with pre-decrement

Load program memory with pre-decrement

Load external data memory with pre-increment

Load program memory with pre-increment

Load word

LDCI

LDEPD

LDCPD

LDEPI

LDCPI

LDW

POP

Pop from stack

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

dst, src

Src

Pop user stack (decrementing)

Pop user stack (incrementing)

Push to stack

dst, src

Push user stack (decrementing)

Push user stack (incrementing)

6-2

S3P80C5/C80C5/C80C8

INSTRUCTION SET

Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Mnemonic

Arithmetic Instructions

ADC

ADD

dst,src

Add with carry

Add

dst,src

dst

Compare

Decimal adjust

Decrement

Decrement word

Divide

DEC

DECW

DIV

dst

dst,src

dst

INC

Increment

INCW

MULT

SBC

SUB

dst

Increment word

Multiply

dst,src

Subtract with carry

Subtract

Logic Instructions

AND

COM

dst,src

dst

Logical AND

Complement

dst,src

Logical OR

XOR

Logical exclusive OR

6-3

INSTRUCTION SET

Mnemonic

S3P80C5/C80C5/C80C8

Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Program Control Instructions

BTJRF

BTJRT

CALL

CPIJE

CPIJNE

DJNZ

ENTER

EXIT

IRET

dst,src

dst

Bit test and jump relative on false

Bit test and jump relative on true

Call procedure

dst,src

r,dst

Compare, increment and jump on equal

Compare, increment and jump on non-equal

Decrement register and jump on non-zero

Enter

Exit

Interrupt return

Jump on condition code

Jump unconditional

Jump relative on condition code

cc,dst

dst

cc,dst

RET

Return

WFI

Wait for interrupt

Bit Manipulation Instructions

BAND

BCP

BITC

BITR

BITS

BOR

BXOR

TCM

dst,src

dst

Bit AND

Bit compare

Bit complement

Bit reset

dst

Bit set

dst,src

Bit OR

Bit XOR

Test complement under mask

Test under mask

6-4

S3P80C5/C80C5/C80C8

Mnemonic

INSTRUCTION SET

Table 6-1. Instruction Group Summary (Concluded)

Operands Instruction

Rotate and Shift Instructions

dst

Rotate left

RLC

Rotate left through carry

Rotate right

RRC

SRA

SWAP

Rotate right through carry

Shift right arithmetic

Swap nibbles

CPU Control Instructions

CCF

Complement carry flag

Disable interrupts

Enable interrupts

Enter Idle mode

No operation

IDLE

NOP

RCF

SB0

SB1

SCF

Reset carry flag

Set bank 0

Set bank 1

Set carry flag

SRP

src

Set register pointers

Set register pointer 0

Set register pointer 1

Enter Stop mode

SRP0

SRP1

STOP

6-5

INSTRUCTION SET

S3P80C5/C80C5/C80C8

FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these

bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and

FLAGS.2 are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank

address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register

can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For

example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND

instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will

occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, Set 1, R/W

MSB

LSB

Bank address

status flag (BA)

Carry flag (C)

First interrupt

status flag (FIS)

Zero flag (Z)

Sign flag (S)

Overflow (V)

Half-carry flag (H)

Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

6-6

S3P80C5/C80C5/C80C8

FLAG DESCRIPTIONS

INSTRUCTION SET

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to

the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the

specified register. Program instructions can set, clear, or complement the carry flag.

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For

operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is

logic zero.

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the

result. A logic zero indicates a positive number and a logic one indicates a negative number.

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than

– 128. It is also cleared to "0" following logic operations.

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a

subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by

programmers, and cannot be used as a test condition.

Half-Carry Flag (FLAGS.2)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows

out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous

addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a

program.

FIS Fast Interrupt Status Flag (FLAGS.1)

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.

When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET

instruction is executed.

BA Bank Address Flag (FLAGS.0)

The BA flag indicates which register bank in the set 1 area of the internal register file is currently

selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0

instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.

6-7

INSTRUCTION SET

S3P80C5/C80C5/C80C8

INSTRUCTION SET NOTATION

Table 6-2. Flag Notation Conventions

Flag

Description

Carry flag

Zero flag

Sign flag

Overflow flag

Decimal-adjust flag

Half-carry flag

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

–

Table 6-3. Instruction Set Symbols

Symbol

dst

src

Description

Destination operand

Source operand

Indirect register address prefix

Program counter

Instruction pointer

FLAGS

Flags register (D5H)

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix

Opcode

opc

6-8

S3P80C5/C80C5/C80C8

Notation

INSTRUCTION SET

Table 6-4. Instruction Notation Conventions

Description Actual Operand Range

Condition code

Working register only

See list of condition codes in Table 6-6.

Rn (n = 0–15)

Bit (b) of working register

Rn.b (n = 0–15, b = 0–7)

Rn (n = 0–15)

Bit 0 (LSB) of working register

Working register pair

RRp (p = 0, 2, 4, ..., 14)

reg or Rn (reg = 0–255, n = 0–15)

reg.b (reg = 0–255, b = 0–7)

Bit 'b' of register or working register

reg or RRp (reg = 0–254, even number only, where

p = 0, 2, ..., 14)

Indirect addressing mode

addr (addr = 0–254, even number only)

@Rn (n = 0–15)

Indirect working register only

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

IRR

Indirect register pair or indirect working

@RRp or @reg (reg = 0–254, even only, where

p = 0, 2, ..., 14)

Indexed addressing mode

#reg [Rn] (reg = 0–255, n = 0–15)

Indexed (short offset) addressing mode

#addr [RRp] (addr = range –128 to +127, where

p = 0, 2, ..., 14)

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 0–65535, where

p = 0, 2, ..., 14)

Direct addressing mode

Relative addressing mode

addr (addr = range 0–65535)

addr (addr = number in the range +127 to –128 that is

an offset relative to the address of the next instruction)

Immediate addressing mode

#data (data = 0–255)

iml

Immediate (long) addressing mode

#data (data = range 0–65535)

6-9

INSTRUCTION SET

S3P80C5/C80C5/C80C8

Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

–

DEC

IR1

ADD

r1,r2

ADD

r1,Ir2

ADD

R2,R1

ADD

IR2,R1

ADD

R1,IM

BOR

r0–Rb

RLC

IR1

ADC

r1,r2

ADC

r1,Ir2

ADC

R2,R1

ADC

IR2,R1

ADC

R1,IM

BCP

r1.b, R2

INC

IR1

SUB

r1,r2

SUB

r1,Ir2

SUB

R2,R1

SUB

IR2,R1

SUB

R1,IM

BXOR

r0–Rb

IRR1

SRP/0/1

SBC

r1,r2

SBC

r1,Ir2

SBC

R2,R1

SBC

IR2,R1

SBC

R1,IM

BTJR

r2.b, RA

IR1

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

LDB

r0–Rb

POP

IR1

AND

r1,r2

AND

r1,Ir2

AND

R2,R1

AND

IR2,R1

AND

R1,IM

BITC

r1.b

COM

IR1

TCM

r1,r2

TCM

r1,Ir2

TCM

R2,R1

TCM

IR2,R1

TCM

R1,IM

BAND

r0–Rb

PUSH

IR2

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

BIT

r1.b

DECW

RR1

DECW

IR1

PUSHUD PUSHUI

IR1,R2

MULT

R2,RR1

MULT

IR2,RR1

MULT

IM,RR1

r1, x, r2

IR1,R2

IR1

POPUD

IR2,R1

POPUI

IR2,R1

DIV

R2,RR1

DIV

IR2,RR1

DIV

IM,RR1

r2, x, r1

INCW

RR1

INCW

IR1

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

LDC

r1, Irr2, xL

CLR

IR1

XOR

r1,r2

XOR

r1,Ir2

XOR

R2,R1

XOR

IR2,R1

XOR

R1,IM

LDC

r2, Irr2, xL

RRC

IR1

CPIJE

Ir,r2,RA

LDC

r1,Irr2

LDW

r1, Ir2

RR2,RR1 IR2,RR1 RR1,IML

SRA

IR1

CPIJNE

Irr,r2,RA

LDC

r2,Irr1

CALL

IA1

IR1,IM

Ir1, r2

IR1

LDCD

r1,Irr2

LDCI

r1,Irr2

R2,R1

R2,IR1

R1,IM

LDC

r1, Irr2, xs

SWAP

IR1

LDCPD

r2,Irr1

LDCPI

r2,Irr1

CALL

IRR1

IR2,R1

CALL

DA1

LDC

r2, Irr1, xs

6-10

S3P80C5/C80C5/C80C8

INSTRUCTION SET

Table 6-5. Opcode Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

–

r1,R2

r2,R1

DJNZ

r1,RA

cc,RA

r1,IM

cc,DA

INC

ENTER

EXIT

WFI

SB0

SB1

IDLE

STOP

RET

IRET

RCF

SCF

CCF

NOP

r1,R2

r2,R1

DJNZ

r1,RA

cc,RA

r1,IM

cc,DA

INC

6-11

INSTRUCTION SET

S3P80C5/C80C5/C80C8

CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under

which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"

after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump

instructions.

Table 6-6. Condition Codes

Binary

Mnemonic

Description

Always false

Flags Set

0000

1000

–

Always true

–

0111 ^(note)

1111 ^(note)

0110 ^(note)

1110 ^(note)

1101

Carry

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

No carry

Zero

Not zero

Plus

0101

Minus

0100

Overflow

1100

NOV

No overflow

Equal

0110 ^(note)

1110 ^(note)

1001

Not equal

Greater than or equal

Less than

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

0001

1010

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

0010

1111 ^(note)

0111 ^(note)

1011

UGE

ULT

UGT

ULE

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

0011

NOTES:

1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For

example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;

after a CP instruction, however, EQ would probably be used.

2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-12

S3P80C5/C80C5/C80C8

INSTRUCTION SET

INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM8

instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.

The following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Specific flag settings affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

6-13

INSTRUCTION SET

S3P80C5/C80C5/C80C8

ADC — Add with carry

ADC

dst,src

Operation:

dst ¬ dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand

and the sum is stored in the destination. The contents of the source are unaffected. Two's-

complement addition is performed. In multiple precision arithmetic, this instruction permits the

carry from the addition of low-order operands to be carried into the addition of high-order

operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result

is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and

ADC R1,R2

R1 = 14H, R2 = 03H

ADC R1,@R2

ADC 01H,02H

ADC 01H,@02H

ADC 01H,#11H

R1 = 1BH, R2 = 03H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",

and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds

03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

6-14

S3P80C5/C80C5/C80C8

INSTRUCTION SET

ADD — Add

ADD

dst,src

Operation:

dst ¬ dst + src

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if a carry from the low-order nibble occurred.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD R1,R2

R1 = 15H, R2 = 03H

ADD R1,@R2

ADD 01H,02H

ADD 01H,@02H

ADD 01H,#25H

R1 = 1CH, R2 = 03H

In the first example, destination working register R1 contains 12H and the source working

in register R1.

6-15

INSTRUCTION SET

S3P80C5/C80C5/C80C8

AND — Logical AND

AND

dst,src

Operation:

dst ¬ dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the

destination. The AND operation results in a "1" bit being stored whenever the corresponding bits

in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the

source are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND R1,R2

R1 = 02H, R2 = 03H

AND R1,@R2

AND 01H,02H

AND 01H,@02H

AND 01H,#25H

R1 = 02H, R2 = 03H

In the first example, destination working register R1 contains the value 12H and the source

working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source

operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

6-16

S3P80C5/C80C5/C80C8

INSTRUCTION SET

BAND — Bit AND

BAND

dst,src.b

BAND

dst.b,src

Operation:

dst(0) ¬ dst(0) AND src(b)

dst(b) ¬ dst(b) AND src(0)

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of

the destination (or source). The resultant bit is stored in the specified bit of the destination. No

other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | b | 0

src | b | 1

src

dst

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four

bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

BAND R1,01H.1

BAND 01H.1,R1

R1 = 06H, register 01H = 05H

In the first example, source register 01H contains the value 05H (00000101B) and destination

working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1

value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the

value 06H (00000110B) in register R1.

6-17

INSTRUCTION SET

S3P80C5/C80C5/C80C8

BCP — Bit Compare

BCP

dst,src.b

Operation:

dst(0) – src(b)

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.

The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both

operands are unaffected by the comparison.

Flags:

C: Unaffected.

Z: Set if the two bits are the same; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | b | 0

src

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H and register 01H = 01H:

BCP

R1,01H.1

R1 = 07H, register 01H = 01H

If destination working register R1 contains the value 07H (00000111B) and the source register

01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of

the source register (01H) and bit zero of the destination register (R1). Because the bit values are

not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

6-18

S3P80C5/C80C5/C80C8

INSTRUCTION SET

BITC — Bit Complement

BITC

dst.b

Operation:

dst(b) ¬ NOT dst(b)

This instruction complements the specified bit within the destination without affecting any other

bits in the destination.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H

BITC R1.1

R1 = 05H

If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"

complements bit one of the destination and leaves the value 05H (00000101B) in register R1.

Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H)

is cleared.

6-19

INSTRUCTION SET

S3P80C5/C80C5/C80C8

BITR— Bit Reset

BITR

dst.b

Operation:

dst(b) ¬ 0

The BITR instruction clears the specified bit within the destination without affecting any other bits

in the destination.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BITR R1.1

R1 = 05H

If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one

of the destination register R1, leaving the value 05H (00000101B).

6-20

S3P80C5/C80C5/C80C8

INSTRUCTION SET

BITS— Bit Set

BITS

dst.b

Operation:

dst(b) ¬ 1

The BITS instruction sets the specified bit within the destination without affecting any other bits

in the destination.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst | b | 1

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BITS R1.3

R1 = 0FH

If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit

three of the destination register R1 to "1", leaving the value 0FH (00001111B).

6-21

INSTRUCTION SET

S3P80C5/C80C5/C80C8

BOR— Bit OR

BOR

dst,src.b

dst.b,src

Operation:

dst(0) ¬ dst(0) OR src(b)

dst(b) ¬ dst(b) OR src(0)

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the

destination (or the source). The resulting bit value is stored in the specified bit of the destination.

No other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | b | 0

src | b | 1

src

dst

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four

bits, the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:

Given: R1 = 07H and register 01H = 03H:

BOR R1, 01H.1

BOR 01H.2, R1

R1 = 07H, register 01H = 03H

In the first example, destination working register R1 contains the value 07H (00000111B) and

source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs

bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value

(07H) in working register R1.

In the second example, destination register 01H contains the value 03H (00000011B) and the

source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically

ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H

in register 01H.

6-22

S3P80C5/C80C5/C80C8

INSTRUCTION SET

BTJRF — Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation:

If src(b) is a "0", then PC ¬ PC + dst

The specified bit within the source operand is tested. If it is a "0", the relative address is added to

the program counter and control passes to the statement whose address is now in the PC;

otherwise, the instruction following the BTJRF instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

(Note 1)

dst

src

opc

src | b | 0

dst

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRF SKIP,R1.3

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"

tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the

memory location pointed to by the SKIP. (Remember that the memory location must be within

the allowed range of + 127 to – 128.)

6-23

INSTRUCTION SET

S3P80C5/C80C5/C80C8

BTJRT— Bit Test, Jump Relative on True

BTJRT

dst,src.b

Operation:

If src(b) is a "1", then PC ¬ PC + dst

The specified bit within the source operand is tested. If it is a "1", the relative address is added to

the program counter and control passes to the statement whose address is now in the PC;

otherwise, the instruction following the BTJRT instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

(Note 1)

dst

src

opc

src | b | 1

dst

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRT

SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"

tests bit one in the source register (R1). Because it is a "1", the relative address is added to the

PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the

memory location must be within the allowed range of + 127 to – 128.)

6-24

S3P80C5/C80C5/C80C8

INSTRUCTION SET

BXOR— Bit XOR

BXOR

dst,src.b

dst.b,src

Operation:

dst(0) ¬ dst(0) XOR src(b)

dst(b) ¬ dst(b) XOR src(0)

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)

of the destination (or source). The result bit is stored in the specified bit of the destination. No

other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | b | 0

src | b | 1

src

dst

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four

bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):

BXOR R1,01H.1

BXOR 01H.2,R1

R1 = 06H, register 01H = 03H

In the first example, destination working register R1 has the value 07H (00000111B) and source

bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in

bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is

unaffected.

6-25

INSTRUCTION SET

S3P80C5/C80C5/C80C8

CALL— Call Procedure

CALL

dst

Operation:

@SP

SP – 1

PCL

SP –1

PCH

dst

The current contents of the program counter are pushed onto the top of the stack. The program

counter value used is the address of the first instruction following the CALL instruction. The

specified destination address is then loaded into the program counter and points to the first

instruction of a procedure. At the end of the procedure the return instruction (RET) can be used

to return to the original program flow. RET pops the top of the stack back into the program

counter.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

IRR

dst

Examples:

Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:

CALL 3521H ®

SP = 0000H

(Memory locations 0000H = 1AH, 0001H = 4AH, where

4AH is the address that follows the instruction.)

SP = 0000H (0000H = 1AH, 0001H = 49H)

CALL @RR0 ®

CALL #40H

In the first example, if the program counter value is 1A47H and the stack pointer contains the

value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the

stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the

value 3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the

statement "CALL @RR0" produces the same result except that the 49H is stored in stack

location 0001H (because the two-byte instruction format was used). The PC is then loaded with

the value 3521H, the address of the first instruction in the program sequence to be executed.

Assuming that the contents of the program counter and stack pointer are the same as in the first

example, if program address 0040H contains 35H and program address 0041H contains 21H, the

statement "CALL #40H" produces the same result as in the second example.

6-26

S3P80C5/C80C5/C80C8

INSTRUCTION SET

CCF— Complement Carry Flag

CCF

Operation:

C ¬ NOT C

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic

zero; if C = "0", the value of the carry flag is changed to logic one.

Flags:

C: Complemented.

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H),

changing its value from logic zero to logic one.

6-27

INSTRUCTION SET

S3P80C5/C80C5/C80C8

CLR— Clear

CLR

dst

Operation:

dst ¬ "0"

The destination location is cleared to "0".

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

CLR

00H

@01H ®

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H

value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)

addressing mode to clear the 02H register value to 00H.

6-28

S3P80C5/C80C5/C80C8

INSTRUCTION SET

COM— Complement

COM

dst

Operation:

dst ¬ NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are

changed to "0s", and vice-versa.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM R1

R1 = 0F8H

R1 = 07H, register 07H = 0EH

COM @R1

In the first example, destination working register R1 contains the value 07H (00000111B). The

statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,

and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value

of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-29

INSTRUCTION SET

S3P80C5/C80C5/C80C8

CP— Compare

dst,src

Operation:

dst – src

The source operand is compared to (subtracted from) the destination operand, and the

appropriate flags are set accordingly. The contents of both operands are unaffected by the

comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst |

src

opc

src

dst

src

Examples:

1. Given: R1 = 02H and R2 = 03H:

CP R1,R2 ® Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the

value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1

value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S

are "1".

2. Given: R1 = 05H and R2 = 0AH:

INC

R1,R2

UGE,SKIP

SKIP LD

R3,R1

In this example, destination working register R1 contains the value 05H which is less than the

contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"

and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"

executes, the value 06H remains in working register R3.

6-30

S3P80C5/C80C5/C80C8

INSTRUCTION SET

CPIJE— Compare, Increment, and Jump on Equal

CPIJE

dst,src,RA

Operation:

If dst – src = "0", PC ¬ PC + RA

Ir ¬ Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is "0",

the relative address is added to the program counter and control passes to the statement whose

address is now in the program counter. Otherwise, the instruction immediately following the

CPIJE instruction is executed. In either case, the source pointer is incremented by one before

the next instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src dst

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 02H:

CPIJE R1,@R2,SKIP ®

R2 = 04H, PC jumps to SKIP location

In this example, working register R1 contains the value 02H, working register R2 the value 03H,

and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value

02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the

relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that

the memory location must be within the allowed range of + 127 to – 128.)

6-31

INSTRUCTION SET

S3P80C5/C80C5/C80C8

CPIJNE— Compare, Increment, and Jump on Non-Equal

CPIJNE

dst,src,RA

Operation:

If dst – src "0", PC ¬ PC + RA

Ir ¬ Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is not

"0", the relative address is added to the program counter and control passes to the statement

whose address is now in the program counter; otherwise the instruction following the CPIJNE

instruction is executed. In either case the source pointer is incremented by one before the next

instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src dst

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 04H:

CPIJNE

R1,@R2,SKIP ®

R2 = 04H, PC jumps to SKIP location

Working register R1 contains the value 02H, working register R2 (the source pointer) the value

03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts

04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal,

the relative address is added to the PC and the PC then jumps to the memory location pointed to

by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.

(Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-32

S3P80C5/C80C5/C80C8

INSTRUCTION SET

DA— Decimal Adjust

dst

Operation:

dst ¬ DA dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or

subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table

indicates the operation performed. (The operation is undefined if the destination operand was not

the result of a valid addition or subtraction of BCD digits):

Instruction

Carry

Before DA

Bits 4–7

Value (Hex)

H Flag

Before DA

Bits 0–3

Value (Hex)

Number Added

to Byte

Carry

After DA

0–9

0–8

0–9

A–F

9–F

A–F

0–2

0–3

0–9

0–8

7–F

6–F

0–9

A–F

0–3

0–9

A–F

0–3

0–9

A–F

0–3

0–9

6–F

0–9

6–F

ADD

ADC

00 = – 00

FA = – 06

A0 = – 60

9A = – 66

SUB

SBC

Flags:

C: Set if there was a carry from the most significant bit; cleared otherwise (see table).

Z: Set if result is "0"; cleared otherwise.

S: Set if result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

6-33

INSTRUCTION SET

S3P80C5/C80C5/C80C8

DA— Decimal Adjust

(Continued)

Example:

Given: Working register R0 contains the value 15 (BCD), working register R1 contains

27 (BCD), and address 27H contains 46 (BCD):

ADD

R1,R0

;

C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = C, R1 ¬ 3CH

R1 ¬ 3CH + 06

If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is

incorrect, however, when the binary representations are added in the destination location using

standard binary arithmetic:

0 0 0 1 0 1 0 1

+ 0 0 1 0 0 1 1 1

0 0 1 1 1 1 0 0

3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:

0 0 1 1 1 1 0 0

+ 0 0 0 0 0 1 1 0

0 1 0 0 0 0 1 0

Assuming the same values given above, the statements

SUB

27H,R0 ;

@R1

C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = 1

@R1 ¬ 31–0

;

leave the value 31 (BCD) in address 27H (@R1).

6-34

S3P80C5/C80C5/C80C8

INSTRUCTION SET

DEC— Decrement

DEC

dst

Operation:

dst ¬ dst – 1

The contents of the destination operand are decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R1 = 03H and register 03H = 10H:

DEC R1

R1 = 02H

DEC @R1

In the first example, if working register R1 contains the value 03H, the statement "DEC R1"

decrements the hexadecimal value by one, leaving the value 02H. In the second example, the

statement "DEC @R1" decrements the value 10H contained in the destination register 03H by

one, leaving the value 0FH.

6-35

INSTRUCTION SET

S3P80C5/C80C5/C80C8

DECW— Decrement Word

DECW

dst

Operation:

dst ¬ dst – 1

The contents of the destination location (which must be an even address) and the operand

following that location are treated as a single 16-bit value that is decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

DECW RR0

DECW @R2

R0 = 12H, R1 = 33H

In the first example, destination register R0 contains the value 12H and register R1 the value

34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word

and decrements the value of R1 by one, leaving the value 33H.

NOTE:

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW

instruction. To avoid this problem, we recommend that you use DECW as shown in the following

example:

LOOP: DECW RR0

R2,R1

R2,R0

NZ,LOOP

6-36

S3P80C5/C80C5/C80C8

INSTRUCTION SET

DI— Disable Interrupts

Operation:

SYM (0) ¬ 0

Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all

interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,

but the CPU will not service them while interrupt processing is disabled.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: SYM = 01H:

If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the

Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

6-37

INSTRUCTION SET

S3P80C5/C80C5/C80C8

DIV— Divide (Unsigned)

DIV

dst,src

Operation:

dst ÷ src

dst (UPPER) ¬ REMAINDER

dst (LOWER) ¬ QUOTIENT

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)

is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of

the destination. When the quotient is ³ 2 , the numbers stored in the upper and lower halves of

the destination for quotient and remainder are incorrect. Both operands are treated as unsigned

integers.

Flags:

C: Set if the V flag is set and quotient is between 2⁸and 2⁹–1; cleared otherwise.

Z: Set if divisor or quotient = "0"; cleared otherwise.

S: Set if MSB of quotient = "1"; cleared otherwise.

V: Set if quotient is ³ 2⁸or if divisor = "0"; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

26/10

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.

Examples:

Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:

DIV

RR0,R2

R0 = 03H, R1 = 40H

R0 = 03H, R1 = 20H

R0 = 03H, R1 = 80H

RR0,@R2

RR0,#20H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H

(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit

RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains

the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the

destination register RR0 (R0) and the quotient in the lower half (R1).

6-38

S3P80C5/C80C5/C80C8

INSTRUCTION SET

DJNZ— Decrement and Jump if Non-Zero

DJNZ

r,dst

Operation:

r ¬ r – 1

If r ¹ 0, PC ¬ PC + dst

The working register being used as a counter is decremented. If the contents of the register are

not logic zero after decrementing, the relative address is added to the program counter and

control passes to the statement whose address is now in the PC. The range of the relative

address is +127 to –128, and the original value of the PC is taken to be the address of the

instruction byte following the DJNZ statement.

NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at

the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

r | opc

dst

8 (jump taken)

8 (no jump)

r = 0 to F

Example:

Given: R1 = 02H and LOOP is the label of a relative address:

SRP

#0C0H

DJNZ R1,LOOP

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the

destination operand instead of a numeric relative address value. In the example, working register

R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.

Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative

address specified by the LOOP label.

6-39

INSTRUCTION SET

S3P80C5/C80C5/C80C8

EI— Enable Interrupts

Operation:

SYM (0) ¬ 1

An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to

be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was

set while interrupt processing was disabled (by executing a DI instruction), it will be serviced

when you execute the EI instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: SYM = 00H:

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the

statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for

global interrupt processing.)

6-40

S3P80C5/C80C5/C80C8

INSTRUCTION SET

ENTER— Enter

ENTER

Operation:

@SP

SP – 2

@IP

IP + 2

This instruction is useful when implementing threaded-code languages. The contents of the

instruction pointer are pushed to the stack. The program counter (PC) value is then written to the

instruction pointer. The program memory word that is pointed to by the instruction pointer is

loaded into the PC, and the instruction pointer is incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

The diagram below shows one example of how to use an ENTER statement.

Before

After

Data

Address

Data

Address

0050

0040

0022

0043

0110

0020

Address

Data

Address

40 Enter

Data

40 Enter

41 Address H 01

42 Address L 10

43 Address H

41 Address H 01

42 Address L 10

43 Address H

IPH

IPL

Data

110 Routine

Memory

Data

Stack

6-41

INSTRUCTION SET

S3P80C5/C80C5/C80C8

EXIT— Exit

EXIT

Operation:

@SP

SP + 2

@IP

IP + 2

This instruction is useful when implementing threaded-code languages. The stack value is

popped and loaded into the instruction pointer. The program memory word that is pointed to by

the instruction pointer is then loaded into the program counter, and the instruction pointer is

incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

14 (internal stack)

16 (internal stack)

Example:

The diagram below shows one example of how to use an EXIT statement.

Before

After

Data

Address

Data

Address

0050

0040

0022

0052

0060

0022

Address

Data

Address

Data

50 PCL old

51 PCH

Main

140 Exit

IPH

IPL

Data

Memory

Data

Stack

6-42

S3P80C5/C80C5/C80C8

INSTRUCTION SET

IDLE— Idle Operation

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle

mode can be released by an interrupt request (IRQ) or an external reset operation.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

–

Example:

The instruction

IDLE

stops the CPU clock but not the system clock.

6-43

INSTRUCTION SET

S3P80C5/C80C5/C80C8

INC— Increment

INC

dst

Operation:

dst ¬ dst + 1

The contents of the destination operand are incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

dst | opc

opc

r = 0 to F

dst

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC

R0 = 1CH

00H

@R0

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement

"INC R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it

contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the

value of register 1BH from 0FH to 10H.

6-44

S3P80C5/C80C5/C80C8

INSTRUCTION SET

INCW— Increment Word

INCW

dst

Operation:

dst ¬ dst + 1

The contents of the destination (which must be an even address) and the byte following that

location are treated as a single 16-bit value that is incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:

INCW RR0

INCW @R1

R0 = 1AH, R1 = 03H

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H

in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the

value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect

00H and register 02H from 0FH to 10H.

NOTE:

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an

INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the

following example:

LOOP:

INCW

RR0

R2,R1

R2,R0

NZ,LOOP

6-45

INSTRUCTION SET

S3P80C5/C80C5/C80C8

IRET— Interrupt Return

IRET

IRET (Normal)

IRET (Fast)

Operation:

FLAGS ¬ @SP

SP ¬ SP + 1

PC ¬ @SP

PC « IP

FLAGS ¬ FLAGS'

FIS ¬

SP ¬ SP + 2

SYM(0) ¬

This instruction is used at the end of an interrupt service routine. It restores the flag register and

the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the

fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast

interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

Bytes

Cycles

Opcode (Hex)

IRET

(Normal)

opc

10 (internal stack)

12 (internal stack)

Bytes

Cycles

Opcode (Hex)

IRET

(Fast)

opc

Example:

In the figure below, the instruction pointer is initially loaded with 100H in the main program

before interrupts are enabled. When an interrupt occurs, the program counter and instruction

pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return

address. The last instruction in the service routine normally is a jump to IRET at address FFH.

This causes the instruction pointer to be loaded with 100H "again" and the program counter to

jump back to the main program. Now, the next interrupt can occur and the IP is still correct at

100H.

FFH

IRET

100H

Interrupt

Service

Routine

JP to FFH

FFFFH

NOTE:

In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay

attention to the order of the last two instructions. The IRET cannot be immediately proceeded by

a clearing of the interrupt status (as with a reset of the IPR register).

6-46

S3P80C5/C80C5/C80C8

INSTRUCTION SET

JP— Jump

cc,dst

(Conditional)

dst

(Unconditional)

Operation:

If cc is true, PC ¬ dst

The conditional JUMP instruction transfers program control to the destination address if the

condition specified by the condition code (cc) is true; otherwise, the instruction following the JP

instruction is executed. The unconditional JP simply replaces the contents of the PC with the

contents of the specified register pair. Control then passes to the statement addressed by the

PC.

Flags:

No flags are affected.

Format: ⁽¹⁾

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(2)

cc | opc

dst

ccD

cc = 0 to F

opc

dst

IRR

NOTES:

1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the

opcode are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

C,LABEL_W

@00H

LABEL_W = 1000H, PC = 1000H

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the

statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to

that location. Had the carry flag not been set, control would then have passed to the statement

immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents

of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-47

INSTRUCTION SET

S3P80C5/C80C5/C80C8

JR— Jump Relative

cc,dst

Operation:

If cc is true, PC ¬ PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the

program counter and control passes to the statement whose address is now in the program

counter; otherwise, the instruction following the JR instruction is executed. (See list of condition

codes).

The range of the relative address is +127, –128, and the original value of the program counter is

taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(1)

cc | opc

dst

ccB

cc = 0 to F

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each

four bits.

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

C,LABEL_X

PC = 1FF7H

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will

pass control to the statement whose address is now in the PC. Otherwise, the program

instruction following the JR would be executed.

6-48

S3P80C5/C80C5/C80C8

INSTRUCTION SET

LD— Load

dst,src

Operation:

dst ¬ src

The contents of the source are loaded into the destination. The source's contents are unaffected.

No flags are affected.

Flags:

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

dst | opc

src | opc

opc

src

dst

r = 0 to F

dst | src

opc

src

dst

src

opc

dst

opc

src

dst

x [r]

dst | src

src | dst

x [r]

6-49

INSTRUCTION SET

S3P80C5/C80C5/C80C8

LD— Load

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,

R0,#10H

R0,01H

R0 = 10H

R0 = 20H, register 01H = 20H

R1 = 20H, R0 = 01H

01H,R0

R1,@R0

@R0,R1

00H,01H

02H,@00H

00H,#0AH

@00H,#10H

@00H,02H

R0 = 01H, R1 = 0AH, register 01H = 0AH

R0 = 0FFH, R1 = 0AH

R0,#LOOP[R1] ®

#LOOP[R0],R1 ®

6-50

S3P80C5/C80C5/C80C8

INSTRUCTION SET

LDB— Load Bit

LDB

dst,src.b

LDB

dst.b,src

Operation:

dst(0) ¬ src(b)

dst(b) ¬ src(0)

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the

source is loaded into the specified bit of the destination. No other bits of the destination are

affected. The source is unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | b | 0

src | b | 1

src

dst

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the

bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0 = 06H and general register 00H = 05H:

LDB

R0,00H.2

00H.0,R0

R0 = 07H, register 00H = 05H

R0 = 06H, register 00H = 04H

In the first example, destination working register R0 contains the value 06H and the source

general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the

00H register into bit zero of the R0 register, leaving the value 07H in register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit

zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in

general register 00H.

6-51

INSTRUCTION SET

S3P80C5/C80C5/C80C8

LDC/LDE— Load Memory

LDC/LDE

dst,src

Operation:

dst ¬ src

This instruction loads a byte from program or data memory into a working register or vice-versa.

The source values are unaffected. LDC refers to program memory and LDE to data memory.

The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd

number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src | dst

dst | src

src | dst

dst | src

Irr

XS [rr]

XL_L

XL_H

DA_H

XL [rr]

XL_L

DA_L

opc

src | dst

dst | 0000

src | 0000

dst | 0001

src | 0001

XL [rr]

10.

opc

NOTES:

1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.

2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one

byte.

3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two

bytes.

4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set

of values, used in formats 9 and 10, are used to address data memory.

6-52

S3P80C5/C80C5/C80C8

INSTRUCTION SET

LDC/LDE— Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations

0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory

locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

LDC

R0,@RR2

; R0 ¬ contents of program memory location 0104H

; R0 = 1AH, R2 = 01H, R3 = 04H

LDE

R0,@RR2

; R0 ¬ contents of external data memory location 0104H

; R0 = 2AH, R2 = 01H, R3 = 04H

LDC ^(note)@RR2,R0

; 11H (contents of R0) is loaded into program memory

; location 0104H (RR2),

; working registers R0, R2, R3 ® no change

LDE

LDC

LDE

@RR2,R0

; 11H (contents of R0) is loaded into external data memory

; location 0104H (RR2),

; working registers R0, R2, R3 ® no change

R0,#01H[RR2]

; R0 ¬ contents of program memory location 0105H

; (01H + RR2),

; R0 = 6DH, R2 = 01H, R3 = 04H

; R0 ¬ contents of external data memory location 0105H

; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H

LDC ^(note)#01H[RR2],R0

; 11H (contents of R0) is loaded into program memory location

; 0105H (01H + 0104H)

LDE

LDC

LDE

#01H[RR2],R0

; 11H (contents of R0) is loaded into external data memory

; location 0105H (01H + 0104H)

R0,#1000H[RR2] ; R0 ¬ contents of program memory location 1104H

; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

R0,#1000H[RR2] ; R0 ¬ contents of external data memory location 1104H

; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

LDC

LDE

R0,1104H

; R0 ¬ contents of program memory location 1104H, R0 = 88H

; R0 ¬ contents of external data memory location 1104H,

; R0 = 98H

LDC ^(note)1105H,R0

; 11H (contents of R0) is loaded into program memory location

; 1105H, (1105H) ¬ 11H

LDE

1105H,R0

; 11H (contents of R0) is loaded into external data memory

; location 1105H, (1105H) ¬ 11H

NOTE: These instructions are not supported by masked ROM type devices.

6-53

INSTRUCTION SET

S3P80C5/C80C5/C80C8

LDCD/LDED— Load Memory and Decrement

LDCD/LDED dst,src

Operation:

dst ¬ src

rr ¬ rr – 1

These instructions are used for user stacks or block transfers of data from program or data

memory to the register file. The address of the memory location is specified by a working register

pair. The contents of the source location are loaded into the destination location. The memory

address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and

external data memory location 1033H = 0DDH:

LDCD

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ¬ RR6 – 1)

LDED

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one (RR6 ¬ RR6 – 1)

; R8 = 0DDH, R6 = 10H, R7 = 32H

6-54

S3P80C5/C80C5/C80C8

INSTRUCTION SET

LDCI/LDEI— Load Memory and Increment

LDCI/LDEI

dst,src

Operation:

dst ¬ src

rr ¬ rr + 1

These instructions are used for user stacks or block transfers of data from program or data

memory to the register file. The address of the memory location is specified by a working register

pair. The contents of the source location are loaded into the destination location. The memory

address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler

makes 'Irr' even for program memory and odd for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)

; R8 = 0CDH, R6 = 10H, R7 = 34H

LDEI

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)

; R8 = 0DDH, R6 = 10H, R7 = 34H

6-55

INSTRUCTION SET

S3P80C5/C80C5/C80C8

LDCPD/LDEPD— Load Memory with Pre-Decrement

LDCPD/

LDEPD

dst,src

Operation:

rr ¬ rr – 1

dst ¬ src

These instructions are used for block transfers of data from program or data memory from the

first decremented. The contents of the source location are then loaded into the destination

location. The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for external data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src | dst

Irr

Examples:

Given: R0 = 77H, R6 = 30H, and R7 = 00H:

LDCPD @RR6,R0

; (RR6 ¬ RR6 – 1)

; 77H (contents of R0) is loaded into program memory location

; 2FFFH (3000H – 1H)

; R0 = 77H, R6 = 2FH, R7 = 0FFH

LDEPD @RR6,R0

; (RR6 ¬ RR6 – 1)

; 77H (contents of R0) is loaded into external data memory

; location 2FFFH (3000H – 1H)

; R0 = 77H, R6 = 2FH, R7 = 0FFH

6-56

S3P80C5/C80C5/C80C8

INSTRUCTION SET

LDCPI/LDEPI— Load Memory with Pre-Increment

LDCPI/

LDEPI

dst,src

Operation:

rr ¬ rr + 1

dst ¬ src

These instructions are used for block transfers of data from program or data memory from the

first incremented. The contents of the source location are loaded into the destination location.

The contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src | dst

Irr

Examples:

Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:

LDCPI

@RR6,R0

; (RR6 ¬ RR6 + 1)

; 7FH (contents of R0) is loaded into program memory

; location 2200H (21FFH + 1H)

; R0 = 7FH, R6 = 22H, R7 = 00H

LDEPI

@RR6,R0

; (RR6 ¬ RR6 + 1)

; 7FH (contents of R0) is loaded into external data memory

; location 2200H (21FFH + 1H)

; R0 = 7FH, R6 = 22H, R7 = 00H

6-57

INSTRUCTION SET

S3P80C5/C80C5/C80C8

LDW— Load Word

LDW

dst,src

Operation:

dst ¬ src

The contents of the source (a word) are loaded into the destination. The contents of the source

are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

src

IML

Examples:

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,

LDW

RR6,RR4

00H,02H

R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH

LDW

RR2,@R7

R2 = 03H, R3 = 0FH,

04H,@01H

RR6,#1234H

02H,#0FEDH

R6 = 12H, R7 = 34H

In the second example, please note that the statement "LDW 00H,02H" loads the contents of

the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in

general register 00H and the value 0FH in register 01H.

The other examples show how to use the LDW instruction with various addressing modes and

formats.

6-58

S3P80C5/C80C5/C80C8

INSTRUCTION SET

MULT— Multiply (Unsigned)

MULT

dst,src

Operation:

dst ¬ dst ´ src

The 8-bit destination operand (even register of the register pair) is multiplied by the source

operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination

address. Both operands are treated as unsigned integers.

Flags:

C: Set if result is > 255; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if MSB of the result is a "1"; cleared otherwise.

V: Cleared.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

MULT

00H, 02H

00H, @01H

00H, #30H

In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in

the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The

16-bit product, 0120H, is stored in the register pair 00H, 01H.

6-59

INSTRUCTION SET

S3P80C5/C80C5/C80C8

NEXT— Next

Operation:

PC ¬ @ IP

IP ¬ IP + 2

The NEXT instruction is useful when implementing threaded-code languages. The program

memory word that is pointed to by the instruction pointer is loaded into the program counter. The

instruction pointer is then incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

The following diagram shows one example of how to use the NEXT instruction.

Before

After

Data

Address

Data

Address

0043

0120

0045

0130

Address

Data

Address

43 Address H

Data

43 Address H 01

44 Address L 10

45 Address H

44 Address L

45 Address H

120 Next

Memory

130 Routine

Memory

6-60

S3P80C5/C80C5/C80C8

INSTRUCTION SET

NOP— No Operation

NOP

Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are

executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

When the instruction

NOP

is encountered in a program, no operation occurs. Instead, there is a delay in instruction

execution time.

6-61

INSTRUCTION SET

S3P80C5/C80C5/C80C8

OR— Logical OR

dst,src

Operation:

dst ¬ dst OR src

The source operand is logically ORed with the destination operand and the result is stored in the

destination. The contents of the source are unaffected. The OR operation results in a "1" being

stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is

stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and

R0,R1

R0 = 3FH, R1 = 2AH

R0,@R2

00H,01H

01H,@00H

00H,#02H

R0 = 37H, R2 = 01H, register 01H = 37H

In the first example, if working register R0 contains the value 15H and register R1 the value

2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the

result (3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing

modes and formats.

6-62

S3P80C5/C80C5/C80C8

INSTRUCTION SET

POP— Pop From Stack

POP

dst

Operation:

dst ¬ @SP

SP ¬ SP + 1

The contents of the location addressed by the stack pointer are loaded into the destination. The

stack pointer is then incremented by one.

Flags:

No flags affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,

and stack register 0FBH = 55H:

POP

00H

@00H

In the first example, general register 00H contains the value 01H. The statement "POP 00H"

loads the contents of location 00FBH (55H) into destination register 00H and then increments the

stack pointer by one. Register 00H then contains the value 55H and the SP points to location

00FCH.

6-63

INSTRUCTION SET

S3P80C5/C80C5/C80C8

POPUD— Pop User Stack (Decrementing)

POPUD

dst,src

Operation:

dst ¬ src

IR ¬ IR – 1

This instruction is used for user-defined stacks in the register file. The contents of the register file

location addressed by the user stack pointer are loaded into the destination. The user stack

pointer is then decremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

Example:

Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and

POPUD 02H,@00H

If general register 00H contains the value 42H and register 42H the value 6FH, the statement

"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The

user stack pointer is then decremented by one, leaving the value 41H.

6-64

S3P80C5/C80C5/C80C8

INSTRUCTION SET

POPUI— Pop User Stack (Incrementing)

POPUI

dst,src

Operation:

dst ¬ src

IR ¬ IR + 1

The POPUI instruction is used for user-defined stacks in the register file. The contents of the

stack pointer is then incremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

Example:

Given: Register 00H = 01H and register 01H = 70H:

POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H

If general register 00H contains the value 01H and register 01H the value 70H, the statement

"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user

stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

6-65

INSTRUCTION SET

S3P80C5/C80C5/C80C8

PUSH— Push To Stack

PUSH

src

Operation:

SP ¬ SP – 1

@SP ¬ src

A PUSH instruction decrements the stack pointer value and loads the contents of the source

(src) into the location addressed by the decremented stack pointer. The operation then adds the

new value to the top of the stack.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

src

8 (internal clock)

8 (external clock)

8 (internal clock)

8 (external clock)

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:

PUSH

40H

SPH = 0FFH, SPL = 0FFH

@40H

0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH

In the first example, if the stack pointer contains the value 0000H, and general register 40H the

value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It

then loads the contents of register 40H into location 0FFFFH and adds this new value to the top

of the stack.

6-66

S3P80C5/C80C5/C80C8

INSTRUCTION SET

PUSHUD— Push User Stack (Decrementing)

PUSHUD

dst,src

Operation:

IR ¬ IR – 1

dst ¬ src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements

the user stack pointer and loads the contents of the source into the register addressed by the

decremented stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst

src

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:

PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The

01H register value, 05H, is then loaded into the register addressed by the decremented user

stack pointer.

6-67

INSTRUCTION SET

S3P80C5/C80C5/C80C8

PUSHUI— Push User Stack (Incrementing)

PUSHUI

dst,src

Operation:

IR ¬ IR + 1

dst ¬ src

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user

stack pointer and then loads the contents of the source into the register location addressed by

the incremented user stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst

src

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:

PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H

pointer.

6-68

S3P80C5/C80C5/C80C8

INSTRUCTION SET

RCF— Reset Carry Flag

RCF

Operation:

C ¬ 0

The carry flag is cleared to logic zero, regardless of its previous value.

C: Cleared to "0".

Flags:

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

6-69

INSTRUCTION SET

S3P80C5/C80C5/C80C8

RET— Return

RET

Operation:

PC ¬ @SP

SP ¬ SP + 2

The RET instruction is normally used to return to the previously executing procedure at the end

of a procedure entered by a CALL instruction. The contents of the location addressed by the

stack pointer are popped into the program counter. The next statement that is executed is the

one that is addressed by the new program counter value.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

8 (internal stack)

10 (internal stack)

Example:

Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:

RET PC = 101AH, SP = 00FEH

The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte

of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the

PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to

memory location 00FEH.

6-70

S3P80C5/C80C5/C80C8

INSTRUCTION SET

RL— Rotate Left

dst

Operation:

C ¬ dst (7)

dst (0) ¬ dst (7)

dst (n + 1) ¬ dst (n), n = 0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7

is moved to the bit zero (LSB) position and also replaces the carry flag.

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

00H

@01H

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)

and setting the carry and overflow flags.

6-71

INSTRUCTION SET

S3P80C5/C80C5/C80C8

RLC— Rotate Left Through Carry

RLC

dst

Operation:

dst (0) ¬ C

C ¬ dst (7)

dst (n + 1) ¬ dst (n), n = 0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The

initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

00H

@01H

In the first example, if general register 00H has the value 0AAH (10101010B), the statement

"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag

and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H

(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

6-72

S3P80C5/C80C5/C80C8

INSTRUCTION SET

RR— Rotate Right

dst

Operation:

C ¬ dst (0)

dst (7) ¬ dst (0)

dst (n) ¬ dst (n + 1), n = 0–6

The contents of the destination operand are rotated right one bit position. The initial value of bit

zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

00H

@01H

In the first example, if general register 00H contains the value 31H (00110001B), the statement

"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to

bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also

resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

6-73

INSTRUCTION SET

S3P80C5/C80C5/C80C8

RRC— Rotate Right Through Carry

RRC

dst

Operation:

dst (7) ¬ C

C ¬ dst (0)

dst (n) ¬ dst (n + 1), n = 0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The

initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit

7 (MSB).

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0" cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC

00H

@01H

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")

replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new

value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both

cleared to "0".

6-74

S3P80C5/C80C5/C80C8

INSTRUCTION SET

SB0— Select Bank 0

SB0

Operation:

BANK ¬ 0

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,

selecting bank 0 register addressing in the set 1 area of the register file.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

The statement

SB0

clears FLAGS.0 to "0", selecting bank 0 register addressing.

6-75

INSTRUCTION SET

S3P80C5/C80C5/C80C8

SB1— Select Bank 1

SB1

Operation:

BANK ¬ 1

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,

selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not

implemented in some KS88-series microcontrollers.)

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

The statement

SB1

sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.

6-76

S3P80C5/C80C5/C80C8

INSTRUCTION SET

SBC— Subtract With Carry

SBC

dst,src

Operation:

dst ¬ dst – src – c

The source operand, along with the current value of the carry flag, is subtracted from the

destination operand and the result is stored in the destination. The contents of the source are

unaffected. Subtraction is performed by adding the two's-complement of the source operand to

the destination operand. In multiple precision arithmetic, this instruction permits the carry

("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of

high-order operands.

Flags:

C: Set if a borrow occurred (src > dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign

of the result is the same as the sign of the source; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and

SBC

R1,R2

R1 = 0CH, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#8AH

R1 = 05H, R2 = 03H, register 03H = 0AH

In the first example, if working register R1 contains the value 10H and register R2 the value 03H,

the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the

destination (10H) and then stores the result (0CH) in register R1.

6-77

INSTRUCTION SET

S3P80C5/C80C5/C80C8

SCF— Set Carry Flag

SCF

Operation:

Flags:

C ¬ 1

The carry flag (C) is set to logic one, regardless of its previous value.

C: Set to "1".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

The statement

SCF

sets the carry flag to logic one.

6-78

S3P80C5/C80C5/C80C8

INSTRUCTION SET

SRA— Shift Right Arithmetic

SRA

dst

Operation:

dst (7) ¬ dst (7)

C ¬ dst (0)

dst (n) ¬ dst (n + 1), n = 0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit

position 6.

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

00H

@02H

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C

flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves

the value 0CDH (11001101B) in destination register 00H.

6-79

INSTRUCTION SET

S3P80C5/C80C5/C80C8

SRP/SRP0/SRP1— Set Register Pointer

SRP

src

SRP0

SRP1

Operation:

If src (1) = 1 and src (0) = 0 then: RP0 (3–7)

src (3–7)

src (4–7),

If src (1) = 0 and src (0) = 1 then: RP1 (3–7)

If src (1) = 0 and src (0) = 0 then: RP0 (4–7)

RP0 (3)

RP1 (4–7)

RP1 (3)

src (4–7),

The source data bits one and zero (LSB) determine whether to write one or both of the register

pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register

pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

src

opc

src

Examples:

The statement

SRP #40H

sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location

0D7H to 48H.

The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to

68H.

6-80

S3P80C5/C80C5/C80C8

INSTRUCTION SET

STOP— Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the

microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,

peripheral registers, and I/O port control and data registers are retained. Stop mode can be

released by an external reset operation or by external interrupts. For the reset operation, the

RESET pin must be held to Low level until the required oscillation stabilization interval has

elapsed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

–

Example:

The statement

STOP

halts all microcontroller operations.

6-81

INSTRUCTION SET

S3P80C5/C80C5/C80C8

SUB— Subtract

SUB

dst,src

Operation:

dst ¬ dst – src

The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. Subtraction is performed by adding the

two's complement of the source operand to the destination operand.

Flags:

C: Set if a "borrow" occurred; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the

sign of the result is of the same as the sign of the source operand; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst |

src

opc

src

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

SUB

R1,R2

R1 = 0FH, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#90H

01H,#65H

R1 = 08H, R2 = 03H

In the first example, if working register R1 contains the value 12H and if register R2 contains the

value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination

value (12H) and stores the result (0FH) in destination register R1.

6-82

S3P80C5/C80C5/C80C8

INSTRUCTION SET

SWAP— Swap Nibbles

SWAP

dst

Operation:

dst (0 – 3) « dst (4 – 7)

The contents of the lower four bits and upper four bits of the destination operand are swapped.

4 3

Flags:

C: Undefined.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:

SWAP

00H

@02H

In the first example, if general register 00H contains the value 3EH (00111110B), the statement

"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value

0E3H (11100011B).

6-83

INSTRUCTION SET

S3P80C5/C80C5/C80C8

TCM— Test Complement Under Mask

TCM

dst,src

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask). The TCM statement complements the destination operand, which is then ANDed with the

source mask. The zero (Z) flag can then be checked to determine the result. The destination and

source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and

TCM

R0,R1

R0 = 0C7H, R1 = 02H, Z = "1"

R0,@R1

00H,01H

00H,@01H

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

TCM

00H,#34

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register

for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one

and can be tested to determine the result of the TCM operation.

6-84

S3P80C5/C80C5/C80C8

INSTRUCTION SET

TM— Test Under Mask

dst,src

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to

determine the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and

R0,R1

R0 = 0C7H, R1 = 02H, Z = "0"

R0,@R1

00H,01H

00H,@01H

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

00H,#54H

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register

for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic

zero and can be tested to determine the result of the TM operation.

6-85

INSTRUCTION SET

S3P80C5/C80C5/C80C8

WFI— Wait For Interrupt

WFI

Operation:

The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take

place during this wait state. The WFI status can be released by an internal interrupt, including a

fast interrupt .

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

( n = 1, 2, 3, … )

Example:

The following sample program structure shows the sequence of operations that follow a "WFI"

statement:

Main program

WFI

(Enable global interrupt)

(Wait for interrupt)

(Next instruction)

Interrupt occurs

Interrupt service routine

Clear interrupt flag

IRET

Service routine completed

6-86

S3P80C5/C80C5/C80C8

INSTRUCTION SET

XOR— Logical Exclusive OR

XOR

dst,src

Operation:

dst ¬ dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is

stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever

the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

dst

src

dst

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and

XOR

R0,R1

R0 = 0C5H, R1 = 02H

R0,@R1

00H,01H

00H,@01H

00H,#54H

R0 = 0E4H, R1 = 02H, register 02H = 23H

In the first example, if working register R0 contains the value 0C7H and if register R1 contains

the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0

value and stores the result (0C5H) in the destination register R0.

6-87

INSTRUCTION SET

S3P80C5/C80C5/C80C8

NOTES

6-88

S3P80C5/C80C5/C80C8

CLOCK CIRCUITS

OVERVIEW

The clock frequency generated for the S3P80C5/C80C5/C80C8 by an external crystal, or supplied by an external

clock source, can range from 1MHz to 4 MHz. The maximum CPU clock frequency, as determined by CLKCON

clock circuit.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal or ceramic resonator oscillation source (or an external clock)

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (f_OSCdivided by 1, 2, 8, or 16)

— Clock circuit control register, CLKCON

XIN

External

Clock

Open Pin

XOUT

Figure 7-1. Main Oscillator Circuit

Figure 7-2. External Clock Circuit

(External Crystal or Ceramic Resonator)

7-1

CLOCK CIRCUITS

S3P80C5/C80C5/C80C8

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by Power On

Reset operation or by a non-vectored interrupt - interrupt with reset (INTR). To enter the Stop mode,

STOPCON (STOP Control register) has to be loaded with value, #0A5H before STOP instruction execution.

After recovering from the Stop mode by reset or interrupt, STOPCON register is automatically cleared.

— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the

interrupt structure, timer 0, and counter A. Idle mode is released by a reset or by an interrupt (external or

internally generated).

STOP

STOPCON

Instruction

CLKCON.3,.4

Oscillator

Stop

1/2

1/8

Main

OSC

CPU

Clock

Oscillator

Wake-up

1/16

Noise

filter

INT Pin ⁽¹⁾

NOTES:

1. An external interrupt with an RC-delay noise filter (for S3C80C5/C80C8/,

INT0-4) is fiexed to release Stop mode and "wake up" the main

oscillator.

2. Because the S3C80C5/C80C8 has no subsystem clock, the 3-bit CLKCON

signature code (CLKCON.2-CLKCON.0) is no meaning.

Figure 7-3. System Clock Circuit Diagram

7-2

S3P80C5/C80C5/C80C8

CLOCK CIRCUITS

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and

has the following functions:

— Oscillator frequency divide-by value

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode

release. (This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. In

S3P80C5/C80C5/C80C8, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in

S3P80C5/C80C5/C80C8.

After a reset, the main oscillator is activated, and the f_OSC/16 (the slowest clock speed) is selected as the CPU

clock. If necessary, you can then increase the CPU clock speed to f_OSC, f_OSC/2, or f_OSC/8.

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

MSB

LSB

Not used

Divide-by selection bits for

CPU clock frequency:

00 = fOSC/16

Not used

01 = fOSC/8

10 = fOSC/2

11 = fOSC (non-divided)

Figure 7-4. System Clock Control Register (CLKCON)

7-3

CLOCK CIRCUITS

S3P80C5/C80C5/C80C8

NOTES

7-4

S3P80C5/C80C5/C80C8

RESET and POWER-DOWN

SYSTEM RESET

S3P80C5/C80C5/C80C8 has four different system reset sources as followings:

— Low Voltage Detect (LVD)

— Internal POR circuit

— INTR (Interrupt with RESET)

— Basic Timer (Watchdog timer)

Enable/Disable

Noise

Filter

LVD

Stop

STOPCON

INTR

POR

BT(WDT)

Figure 8-1. Reset Block Diagram

LVD RESET

The Low Voltage detect circuit is built on the S3P80C5/C80C5/C80C8 product for system reset not in stop mode.

When the operating status is not stop mode it detects a slope of V_DDby comparing the voltage at V_DDwith V_LVD

(Low level Detect Voltage). The reset pulse is generated by the rising slope of V_DD. While the voltage at V_DDis

rising up and passing V_LVD, the reset pulse is occurred at the moment ”V_DD>= V_LVD". This function is disabled

when the operating state is "stop mode" to reduce the current consumption under 1 uA instead of 6 uA.

8-1

RESET and POWER-DOWN

S3P80C5/C80C5/C80C8

INTERRUPT WITH RESET(INTR)

A non vectored interrupt called Interrupt with reset (INTR) is built in

S3C80C5/C80C8 to release stop status with system reset. When a falling/rising edge occurs at Port 0 during stop

mode, INTR signal is generated and it makes the system reset pulse. An INTR signal is generated relating to

interaction between Port 0 and operating status. It is enabled by STOP status and occurs by falling/rising edge at

port0. So only when the chip status is "STOP", it is available. If the operating status is not stop status INTR does

not occurs.

NOTE

This INTR is supplementary function to make system reset for an application which is using " stop mode"

like remote controller. If an application which is not using "stop mode" , INTR function can be discarded.

WATCHDOG TIMER RESET

The S3P80C5/C80C5/C80C8 build a watch-dog timer that can recover to normal operation from abnormal

function. Watchdog timer generates a system reset signal if not clearing a BT-Basic Counter within a specific

time by program. System reset can return to the proper operation of chip.

POWER-ON RESET(POR)

The power-on reset circuit is built on the S3P80C5/C80C5/C80C8 product. During a power-on reset, the voltage

at V_DDgoes to High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High

level. The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the

Schmitt trigger input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal

capacitor, and a Schmitt trigger input transistor.

VDD

R : On-Chip Resistor

C : On-Chip Capacitor

System Reset

Schmitt Trigger Inverter

VSS

Figure 8-2. Power-on Reset Circuit

8-2

S3P80C5/C80C5/C80C8

RESET and POWER-DOWN

If Va voltage is under the 0.4 VDD, Reset pulse signal is gernerated.

If Va voltage is over than 0.4 VDD, Reset pulse is not gernerated.

TVDD

(VDD Rising Time)

Voltage [V]

VDD

VIH = 0.85 VDD

VIL = 0.4 VDD

Reset Pulse Width

Reset pulse

Time

Figure 8-3. Timing Diagram for Power-on Reset Circuit

SYSTEM RESET OPERATION

System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal

CPU and peripheral modules. This procedure brings the S3P80C5/C80C5/C80C8 into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level

for a minimum time interval after the power supply comes within tolerance. The minimum required reset

operation for a oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are

then reset to their default hardware values (see Tables 5-1).

In summary, the following sequence of events occurs during a reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0, 1 and 2 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.

— Peripheral control and data register settings are disabled and reset to their default hardware values (see

Table 5-1).

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM

location 0100H (and 0101H) is fetched and executed.

8-3

RESET and POWER-DOWN

S3P80C5/C80C5/C80C8

HARDWARE RESET VALUES

Tables 5-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data

registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An 'x' means that the bit value is undefined after a reset.

— A dash ('-') means that the bit is either not used or not mapped (but a 0 is read from the bit position)

Table 8-1. Set 1 Register Values After Reset

Mnemonic

Address

Dec

Bit Values After Reset

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

–

Timer 0 counter (read-only)

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

208

209

210

211

212

213

214

215

–

RP1

Location D8H (SPH) is not mapped.

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register (read-only)

Interrupt mask register

System mode register

SPL

IPH

IPL

IRQ

IMR

SYM

217

218

219

220

221

222

223

224

225

226

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

–

Port 0 data register

Port 1 data register

Port 2 data register

Location E3H–E6H is not mapped.

Port 0 pull-up enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

P0PUR

P0CONH

P0CONL

231

232

233

E7H

E8H

E9H

8-4

S3P80C5/C80C5/C80C8

RESET and POWER-DOWN

Table 8-1. Set 1 Register Values After Reset (Continued)

Mnemonic

Address

Bit Values After Reset

Dec

Hex

EAH

EBH

ECH

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 1 pull-up enable register

P1CONH

P1CONL

P1PUR

234

235

236

Location EDH–EFH is not mapped.

Port 2 control register

P2CON

P0INT

240

241

242

243

244

245

246

247

248

249

250

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

–

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

P0PND

CACON

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

T1DATAL

T1CON

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)

Timer 1 control register

Stop control register

STOPCON 251

Locations FCH is not mapped.

Basic timer counter

BTCNT

EMT

253

254

255

FDH

FEH

FFH

External memory timing register

Interrupt priority register

–

IPR

NOTES:

1. Although the SYM register is not used for the S3P80C5/C80C5/C80C8, SYM.5

should always be "0". If you accidentally write a 1 to this bit during normal operation, a system malfunction may occur.

2. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are

read/write addressable.

3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.

4. Interrupt pending flags are noted by shaded table cells.

8-5

RESET and POWER-DOWN

S3P80C5/C80C5/C80C8

POWER-DOWN MODES

STOP MODE

Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the

operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply

current is reduced to less than 3 uA at 5.5 V. All system functions stop when the clock "freezes,"

Stop mode can be released of two ways : by an INTR (Interrupt with Reset) or by a POR (Power On Reset).

USING POR TO RELEASE STOP MODE

Stop mode is released when the reset signal goes active by power on reset (POR): all system and peripheral

control registers are reset to their default hardware values and the contents of all data registers are unknown

states. When the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by

fetching the program instruction stored in ROM location 0100H.

USING AN INTR TO RELEASE STOP MODE

Stop mode is released when INTR (Interrupt with Reset) occurs. INTR occurs when falling/rising edge is detected

at P0 during stop mode and it make system reset.

NOTE

1. Do not use stop mode if you are using an external clock source because X_INinput must be cleared

internally to V_SSto reduce current leakage.

2. STOP mode always be released by the system reset (INTR or POR) so the system register value and

control register value are initialized as reset value. And when the reset occurs from INTR, the prime

which is using stop mode should be added specific S/W which divide the system reset into STOP

mode releasing or power on reset. Following Programming Tip can be useful for more

understanding.

8-6

S3P80C5/C80C5/C80C8

RESET and POWER-DOWN

PROGRAMMING TIP — To Divide STOP Mode Releasing and POR.

This example shows how to enter the stop mode and how to know it is stop mode releasing or power on RESET.

ORG

0100H

; Reset address

START

;

BTCON,#03h

SPL,#0FFH

SYM

; enable basic timer counter.

; Initialize the system register

CLR

EMT

IPR

•

P0CONH,#00H

P0CONL,#00H

P0PUR,#0FFH

; Initialize the control register

•

CHECK_RAM:

CHK_R

; Check the RAM data whether it is stop mode releasing

; or Power On RESET

R0,#0BFH

; If Power On Reset , go to POR_RESET

R0,@R0

;

NE,POR_RESET

DEC

R0,#0B0H

UGE, CHK_R

STOP_RESET:

; STOP mode releasing.

;

MAIN

POR_RESET LD

R0,#0FFH

;Power On Reset

;CHECK RAM data are failed so clear all RAM data.

RAM_CLR

CLR

@R0

DJNJ

R0,RAMCLR

R0,#0BFH

;Initialize the CHECK RAM data as default value .

8-7

RESET and POWER-DOWN

S3P80C5/C80C5/C80C8

PROGRAMMING TIP — To Divide STOP Mode Releasing and POR. (Continued)

CHK_W

@R0,R0

DEC

R0,#0B0H

UGE,CHK_W

MAIN:

•

P0,#0FFH

;

EQ,ENT_STOP

•

T,MAIN

ENT_STOP

STOPCON,#0A5H

;Enter the STOP mode.

STOP

NOP

RESET

•

8-8

S3P80C5/C80C5/C80C8

IDLE MODE

RESET and POWER-DOWN

Idle mode is invoked by the instruction IDLE (OPCODE 6FH). In Idle mode, CPU operations are halted while

some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU and from

all but the following peripherals, which remain active:

— Interrupt logic

— Timer 0

— Timer 1

— Counter A

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents

of all data registers are retained. The reset automatically selects the slowest clock because of the hardware

reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the

only way you can release Idle mode.

2. Activate any enabled interrupt ; internal or external. When you use an interrupt to release Idle mode, the 2-bit

CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The

interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately

following the one which initiated Idle mode is executed.

NOTE

Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode

without reset. To release Idle mode, you can use either an external interrupt or an internally-generated

interrupt.

8-9

RESET and POWER-DOWN

S3P80C5/C80C5/C80C8

SUMMARY TABLE OF STOP MODE, AND IDLE MODE

Table 8-2. Summary of Each Mode

IDLE

V_DDis higher than V_LVD(V_LVD< V_DD).

Item/Mode

STOP

Approach Condition

V_DDis higher than V_LVD(V_LVD< V_DD).

IDLE (instruction).

STOPCON £ A5H

STOP instruction

Release Source

Interrupt

RESET

INTR

T0/T1 interrupt

Counter A interrupt

Ext. interrupt (Port0)

POR

RESET

POR

LVD

WDT

8-10

S3P80C5/C80C5/C80C8

I/O PORTS

OVERVIEW

The S3P80C5/C80C5/C80C8 microcontroller has three bit-programmable I/O ports, P0–P2. Two ports, P0-P1,

are 8-bit ports and P2 is a 3-bit port. This gives a total of 19 I/O pins in the S3P80C5/C80C5/C80C8"s 24-pin

package. Each port is bit-programmable and can be flexibly configured to meet application design requirements.

The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.

For IR universal remote controller applications, ports 0, and1 are usually configured to the keyboard matrix and

port 2 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a LED.

Table 9-1 gives you a general overview of S3P80C5/C80C5/C80C8 I/O port functions.

Table 9-1. S3P80C5/C80C5/C80C8 Port Configuration Overview

Port

Configuration Options

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling

edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt

enable/disable (P0INT) and pending control (P0PND); Pull-up resistors can be assigned to

individual P0 pins using P0PUR register settings. Specially Interrupt with Reset(INTR) is

assigned to release stop mode with system reset.

8-bit general-purpose I/O port; Input, open-drain output, or push-pull output. Pull-up resistors

can be assigned to individual P1 pins using P1PUR register settings.

3-bit I/O port; input mode with or without pull-up, push-pull or open-drain output mode. REM

and T0PWM can be assigned. Port 2 pins have high current drive capability to support LED

applications. The port 2 data register contains three status bits: three for P2.0, P2.1 and P2.2

and one for remote controller carrier signal on/off status.

9-1

I/O PORTS

S3P80C5/C80C5/C80C8

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all three S3C80C5/C80C8 port data registers. Data

registers for ports 0, and 1 have the general format.

NOTE

The data register for port 2, P2, contains three bits for P2.0, P2.1 and P2.2, and an additional status bit

for carrier signal on/off.

Table 9-2. Port Data Register Summary

Port 0 data register

Port 1 data register

Port 2 data register

Mnemonic

Decimal

224

Hex

E0H

E1H

E2H

R/W

225

226

Because port 2 is a 3-bit I/O port, the port 2 data register only contains values for P2.0, P2.1 and P2.2. The P2

bit(P2.5). See the port 2 description for details. All other S3P80C5/C80C5/C80C8 I/O ports are 8-bit.

PULL-UP RESISTOR ENABLE REGISTERS

Port0 Pull-up Resistor Enable Register (P0PUR)

E7H, R/W

MSB .7

LSB

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

Pull-up resistor enable bit:

0 = Enable pull-up resistor

1 = Disable pull-up resistor

NOTE:

Pull-up resistors can be assigned to the port 2 pins, P2.0, P2.1 and

P2.2 by marking the appropriate the port 2 control register,P2CON.

Figure 9-1. S3P80C5/C80C5/C80C8 I/O Port 0 Data Register Format

9-2

S3P80C5/C80C5/C80C8

I/O PORTS

Port1 Pull-up Resistor Enable Register (P1PUR)

ECH, R/W

MSB

.0 LSB

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Pull-up resistor enable bit:

0 = Disable pull-up resistor

1 = Enable pull-up resistor

NOTE:

Pull-up resistors can be assigned to the port 2 pins, P2.0, P2.1 and P2.2

by marking the appropriate the port 2 control register, P2CON.

Figure 9-2. S3P80C5/C80C5/C80C8 I/O Port 1 Data Register Format

9-3

I/O PORTS

PORT 0

S3P80C5/C80C5/C80C8

Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write

operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment

using P0PUR register settings and all pins have noise filters for external interrupt inputs.

Two 8-bit control registers are used to configure port 0 pins: P0CONH (set 1, E8H) for the upper nibble pins,

P0.7–P0.4, and P0CONL (set 1, E9H) for lower nibble pins, P0.3–P0.0. Each control register byte contains four

bit-pairs and each bit-pair configures one pin (see Figures 9-2 and 9-3). A hardware reset clears all P0 control

and data registers to '00H'.

A separate register, the port 0 interrupt control register, P0INT (set 1, F1H), is used to enable and disable

external interrupt input. You can poll the port 0 interrupt pending register, P0PND to detect and clear pending

conditions for these interrupts.

The lower-nibble pins, P0.3–P0.0, are used for INT3–INT0 input (IRQ6), respectively. The upper nibble pins,

P0.7–P0.4, are all used for INT4 input (IRQ7). Interrupts that are detected at any of these four pins are processed

using the same vector address (E8H).

Port 0 , P0.0–P0.7, is assigned interrupt with reset(INTR) to release stop mode with system reset.

Port 0 Control Register, High Byte (P0CONH)

E8H, Set 1, R/W

MSB

LSB

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

P0CONH Pin Configureation Settings:

00 Input mode; interrupt on falling edges

01 Input mode; interrupt on rising and falling edges

10 Push-pull output mode

11 Input mode; interrupt on rising edges

Figure 9-3. Port 0 High-Byte Control Register (P0CONH)

9-4

S3P80C5/C80C5/C80C8

I/O PORTS

Port 0 Control Register, Low Byte (P0CONL)

E9H, Set 1, R/W

MSB

LSB

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

P0CONL Pin Configureation Settings:

00 Input mode; interrupt on falling edges

01 Input mode; interrupt on rising and falling edges

10 Push-pull output mode

11 Input mode; interrupt on rising edges

Figure 9-4. Port 0 Low-Byte Control Register (P0CONL)

PORT 0 INTERRUPT ENABLE REGISTER (P0INT)

The port 0 interrupt control register, P0INT, is used to enable and disable external interrupt input at individual P0

pins (see Figure 10-5). To enable a specific external interrupt, you set its P0INT.n bit to "1". You must also be

sure to make the correct settings in the corresponding port 0 control register (P0CONH, P0CONL).

PORT 0 INTERRUPT PENDING REGISTER (P0PND)

The port 0 interrupt pending register, P0PND, contains pending bits (flags) for each port 0 interrupt (see Figure

10-6). When a P0 external interrupt is acknowledged by the CPU, the service routine must clear the pending

condition by writing a "0" to the appropriate pending flag in the P0PND register (Writing a "1" to the pending bit

has no effect).

NOTE

A hardware reset(INTR, POR) clears the P0INT and P0PND registers to '00H'. For this reason, the

application program's initialization routine must enable the required external interrupts for port 0, and for

the other I/O ports.

9-5

I/O PORTS

S3P80C5/C80C5/C80C8

Port 0 Interrup Enable Register (P0INT)

F1H, Set 1, R/W

MSB

LSB

P0.6/INT4

P0.4/INT4

P0.2/INT2

P0.0/INT0

P0.7/INT4

P0.5/INT4

P0.3/INT3

P0.1/INT1

Port 0 Interrupt Enable Bits:

Disable interrupt

Enable interrupt

Figure 9-5. Port 0 External Interrupt Control Register (P0INT)

Port 0 Interrup Pending Register (P0PND)

F2H, Set 1, R/W

MSB

LSB

P0.6/INT4

P0.4/INT4

P0.2/INT2

P0.0/INT0

P0.7/INT4

P0.5/INT4

P0.3/INT3

P0.1/INT1

Port 0 Interrupt Pending Bits:

Interrupt not pending

Clear P0.n pending condition (when write)

P0.n interrupt is pending

No effect (when write)

Figure 9-6. Port 0 External Interrupt Pending Register (P0PND)

9-6

S3P80C5/C80C5/C80C8

PORT 1

I/O PORTS

Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1

data register, P1 (set 1, E1H).

To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers:

P1CONH (set 1, EAH) for the upper nibble pins, P1.7–P1.4, and P1CONL (set 1, EBH) for the lower nibble pins,

P1.3–P1.0. Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see

Figures 9-6 and 9-7).

Following a hardware reset, the port 1 control registers are cleared to '00H', configuring port 0 initially to Input

mode.

To assign pull-up resistors to P1 pins, you make the appropriate settings to the port 1 pull-up resistor enable

Port 1 Control Register, High Byte (P1CONH)

EAH, Set 1, R/W

MSB

LSB

P1.4

P1.5

P1.6

P1.7

P1CONH Pin Configureation Settings:

00 Input mode

01 Open-drain output mode

10 Push-pull output mode

11 Invalid setting

Figure 9-7. Port 1 High-Byte Control Register (P1CONH)

9-7

I/O PORTS

S3P80C5/C80C5/C80C8

Port 1 Control Register, Low Byte (P1CONL)

EBH, Set 1, R/W

MSB

LSB

P1.0

P1.1

P1.2

P1.3

P1CONL Pin Configureation Settings:

00 Input mode

01 Open-drain output mode

10 Push-pull output mode

11 Invalid setting

Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)

9-8

S3P80C5/C80C5/C80C8

PORT 2

I/O PORTS

Port 2 is a bit-programmable 3-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2

data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode,

or push-pull output mode.

P2.0, P2.1 and P2.2 are configured by writing 6-bit data value to the port 2 control register, P2CON. You can

configure these pins to support input functions (Input mode, with or without pull-up, for T0CK) or output functions

(push-pull or open-drain output mode for REM and timer 0 PWM).

Port 2 pins have high current drive capability to support LED applications.

A reset operation clears P2CON to '00H', selecting Input mode as the initial port 2 function.

Port 2 Control Register (P2CON)

F0H, R/W

MSB

LSB

P1.0

P2.2

P2.1

P2.2

P2.1 Alternative Function Enable

Normal I/O Function

REM/T0CK

P2.0 Alternative Function Enable

Normal I/O Function

T0PWM

P2CON Pin Configuration Setting:

00 C-MOS input mode

01 Open-drain output mode

10 Push-pull output mode

11 C-MOS input mode with pull-up

Figure 9-9. Port 2 Control Register (P2CON)

9-9

I/O PORTS

S3P80C5/C80C5/C80C8

Port 2 Data Register (P2)

E2H, R/W

MSB

LSB

P2.0/T0_PWM

P2.1/REM/TOCK

Not used for S3C80C5

Carrier on/off for Remote Controller

P2.2

Not used for S3C80C5

Figure 9-10. Port 2 Data Register (P2)

9-10

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

10 BASIC TIMER and TIMER 0

MODULE OVERVIEW

The S3P80C5/C80C5/C80C8 has two default timers: an 8-bit basic timer and one 8-bit general-purpose

timer/counter. The 8-bit timer/counter is called timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or

— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer

counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,

address D3H, and is read/write addressable using Register addressing mode.

A system reset clears BTCON. This enables the watchdog function and selects a basic timer clock frequency of

f_OSC/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer

function in remote controller and hand-held product application.

10-1

BASIC TIMER and TIMER 0

S3P80C5/C80C5/C80C8

Basic Timer Control Register (BTCON)

D3H, Set 1, R/W

MSB

LSB

Watchdog function enable bits:

1010B = Disable watchdog timer

Other value = Enable watchdog timer

Divider clear bit for basic

timer and timer 0:

0 = No effect

1 = Clear both dividers

Basic timer input clock selection bits:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00 fOSC/4096

01 fOSC/1024

10 fOSC/128

11 Invalid selection

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by enabling the watchdog function.

A reset clears BTCON to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU

clock (as determined by the current CLKCON register setting),divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must

prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must

be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation

will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal

operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always

broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 overflow interrupt or timer 0 match interrupt

— Clear timer 0 match interrupt pending conditions

T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.

A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency

of f_OSC/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal

operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address FAH. When a timer 0

overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer 0 match interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a match

interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a timer 0 match

interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by

software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.

10-3

BASIC TIMER and TIMER 0

S3P80C5/C80C5/C80C8

Timer 0 Control Register (T0CON)

D2H, Set 1, R/W

MSB

LSB

Timer 0 match interrupt pending bit:

0 = No interrupt pending

Timer 0 input clock selection bits:

00 = fOSC/4096

0 = Clear pending bit (write)

1 = Interrupt is pending

01 = fOSC/256

10 = fOSC/8

11 = External clock (P2.1/T0CK)

Timer 0 match interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 0 operating mode selection bits:

00 = Interval mode

01 = Overflow mode (OVF interrupt can occur)

10 = Overflow mode (OVF interrupt can occur)

11 = PWM mode (OVF interrupt can occur)

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Figure 10-2. Timer 0 Control Register (T0CON)

10-4

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)

The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match

interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0, but is

assigned the separate vector address, FCH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.

The T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a

"0" to the T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)

and clears the counter.

If, for example, you write the value ‘10H’ to T0DATA and ‘0BH’ to T0CON, the counter will increment until it

reaches ‘10H’. At this point, the T0 interrupt request is generated, the counter value is reset, and counting

resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).

IRQ0(INT)

Pending

(T0CON.0)

Interrupt

Enable/Disable

(T0CON.1)

R (Clear)

CLK

Counter

Match

Comparator

Buffer Register

CTL

P2.0

T0CON.5

T0CON.4

Match Signal

T0CON.3

Data Register

Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode

10-5

BASIC TIMER and TIMER 0

S3P80C5/C80C5/C80C8

Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the

value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at ‘FFH’, and then continues incrementing from ‘00H’.

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used

in PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference

data value is less than or equal to ( £ ) the counter value and then the pulse is held to High level for as long as

the data value is greater than ( > ) the counter value. One pulse width is equal to t_CLK´ 256 (see Figure 11-4).

IRQ0(T0INT)

PND (T0CON.0)

Interrupt

Enable/Disable

(T0CON.1)

CLK

Counter

IRQ0 (T0OVF)

CTL

High level when

data > counter;

Match

P2.0/

Comparator

Buffer Register

T0PWM Low level when

data < counter

T0CON.5

T0CON.4

Match Signal

T0CON.3

T0OVF

Data Register

NOTE: Interrupts are usually not used when timer 0 is configurared to operate in PWM mode

Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode

10-6

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

Bit 1

RESET

or Stop

Basic Timer Control Register

(Write '1010xxxxB' to disable)

Bits 3,2

MUX

Data Bus

Clear

1/4096

RESET

8-Bit Basic Counter

(Read-Only)

1/1024

1/128

OVF

DIV

XIN

Bit 2

Bit 0

Bits 7,6

MUX

OVF

Bit 3

Clear

Data Bus

1/4096

1/1024

1/128

8-Bit Up-Counter

(Read-Only)

DIV

(2)

Match

T0CON.0

PND

P2.1/T0CK

8-Bit Comparator

Bit 1

T0INT

T0PWM

P2.0

Timer 0 Buffer Reg

Bits 5,4

Match Signal

T0CON.3

T0OVF

Basic Timer Control Register

Timer 0 Control Register

Timer 0 Data Register

(Read/Write)

Data Bus

NOTES:

1. During a power-on reset operation, the CPU is idle during the required oscillation

stabilizatiin interval (until bit 4 of the basic timer counter overflows).

2. It is available only in using interval mode.

Figure 10-5. Basic Timer and Timer 0 Block Diagram

10-7

BASIC TIMER and TIMER 0

S3P80C5/C80C5/C80C8

PROGRAMMING TIP — Configuring the Basic Timer

This example shows how to configure the basic timer to sample specifications:

ORG

0100H

RESET

; Disable all interrupts

BTCON,#03H

CLKCON,#18H

SYM

; Enable the watchdog timer

; Non-divided clock

CLR

; Disable global and fast interrupts

; Stack pointer low byte ¬ "0"

; Stack area starts at 0FFH

SPL

•

SRP

#0C0H

; Set register pointer ¬ 0C0H

•

; Enable interrupts

•

MAIN

BTCON,#02H

; Enable the watchdog timer

; Basic timer clock: f_OSC/4096

; Clear basic timer counter

NOP

•

T,MAIN

•

10-8

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

Programming Tip — Programming Timer 0

This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and

determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:

— Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds

— Oscillation frequency is 4 MHz

— General register 60H (page 0) ¬ 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0

interrupt

ORG

0FAH

; Timer 0 overflow interrupt

; Timer 0 match/capture interrupt

0100H

VECTOR

ORG

T0OVER

0FCH

T0INT

ORG

VECTOR

RESET

; Disable all interrupts

BTCON,#0AAH

CLKCON,#18H

SYM

; Disable the watchdog timer

; Select non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte ¬ "0"

; Stack area starts at 0FFH

CLR

SPL

•

T0CON,#4BH

; Write '01001011B'

; Input clock is f_OSC/256

; Interval timer mode

; Enable the timer 0 interrupt

; Disable the timer 0 overflow interrupt

; Set timer interval to 4 milliseconds

; (4 MHz/256) ¸ (93 + 1) = 0.166 kHz (6 ms)

T0DATA,#5DH

#0C0H

SRP

; Set register pointer ¬ 0C0H

•

; Enable interrupts

•

10-9

BASIC TIMER and TIMER 0

S3P80C5/C80C5/C80C8

PROGRAMMING TIP — Programming Timer 0 (Continued)

T0INT

PUSH

SRP0

INC

RP0

; Save RP0 to stack

; RP0 ¬ 60H

#60H

; R0 ¬ R0 + 1

ADD

ADC

R2,R0

R3,R2

R4,R0

; R2 ¬ R2 + R0

; R3 ¬ R3 + R2 + Carry

; R4 ¬ R4 + R0 + Carry

R0,#32H

; 50 ´ 6 = 300 ms

ULT,NO_300MS_SET

R1.2

BITS

; Bit setting (61.2H)

NO_300MS_SET:

T0CON,#42H

RP0

; Clear pending bit

POP

; Restore register pointer 0 value

T0OVER

IRET

; Return from interrupt service routine

10-10

S3P80C5/C80C5/C80C8

TIMER 1

11 TIMER 1

OVERVIEW

The S3C80C5/C80C8 microcontroller has a 16-bit timer/counter called timer 1 (T1). For universal remote

controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal.

Timer 1 has the following components:

— One control register, T1CON (set 1, FAH, R/W)

— Two 8-bit counter registers, T1CNTH and T1CNTL (set 1, F6H and F7H, read-only)

— Two 8-bit reference data registers, T1DATAH and T1DATAL (set 1, F8H and F9H, R/W)

— A 16-bit comparator

You can select one of the following clock sources as the timer 1 clock:

— Oscillator frequency (f_OSC) divided by 4, 8, or 16

— Internal clock input from the counter A module (counter A flip/flop output)

You can use Timer 1 in two ways:

— As a normal free run counter, generating a timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time

intervals.

— To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the

16-bit value written to the reference data registers.

In the S3C80C5/C80C8 interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1

match.

11-1

TIMER 1

S3P80C5/C80C5/C80C8

TIMER 1 OVERFLOW INTERRUPT

Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the

16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt

is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the

counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.3, you can

clear/reset the 16-bit counter value at any time during program operation.

TIMER 1 MATCH INTERRUPT

Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value

matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a

match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is

cleared, and up counting resumes from ‘00H’.

In match mode, program software can poll the timer 1 match interrupt pending bit, T1CON.0, to detect when a

timer 1 match interrupt pending condition exists (T1CON.0 = "1"). When the interrupt request is acknowledged by

the CPU and the service routine starts, the interrupt service routine for vector F6H must clear the interrupt

pending condition by writing a “0” to T1CON.0.

IRQ1(T1INT)

Pending

(T1CON.0)

Interrupt

Enable/Disable

(T1CON.2)

R (Clear)

Match

16-Bit UP Counter

(Read-Only)

CLK

16-Bit Comparator

CTL

T1CON.5

T1CON.4

Timer 1 High/Low

Buffer Register

Match Signal

T1CON.3

Timer 1 Data High/Low

Buffer Register

Figure 11-1. Simplified Timer 1 Function Diagram: Interval Timer Mode

11-2

S3P80C5/C80C5/C80C8

TIMER 1

T1CON.2

T1CON.7-.6

OVF

IRQ1

CAOF (T-F/F)

fOSC/4

T1CON.3

Clear

16-Bit Up-Counter

(Read-Only)

MUX

fOSC/8

Match^(note)

fOSC/16

16-Bit Comparator

T1CON.1

T1CON.5-.4

T1CON.0

IRQ1

Timer 1 High/Low

Buffer Register

T1CON.3

Match Signal

T1OVF

Timer 1 Data

High/Low Register

Data Bus

NOTES: Match signal is occured only in interval mode.

Figure 11-2. Timer 1 Block Diagram

11-3

TIMER 1

S3P80C5/C80C5/C80C8

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains

control settings for the following T1 functions:

— Timer 1 input clock selection

— Timer 1 operating mode selection

— Timer 1 16-bit down counter clear

— Timer 1 overflow interrupt enable/disable

— Timer 1 match interrupt enable/disable

— Timer 1 interrupt pending control (read for status, write to clear)

A reset operation clears T1CON to ‘00H’, selecting f

divided by 4 as the T1 clock, configuring timer 1 as a

normal interval timer, and disabling the timer 1 interrupts.

OSC

Timer 1 Control Register (T1CON)

FAH, R/W

MSB

LSB

Timer 1 match interrupt pending bit:

0 = No interrupt pending

Timer 1 input clock selection bits:

00 = fOSC/4

0 = Clear pending bit (write)

1 = Interrupt is pending

01 = fOSC/8

10 = fOSC/16

11 = Internal clock (T-F/F)

Timer 1 match interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 1 operating mode selection bits:

00 = Interval mode

01 = Overflow mode (OVF interrupt can occur)

Timer 1 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer 1 counter (when write)

Figure 11-3. Timer 1 Control Register (T1CON)

11-4

S3P80C5/C80C5/C80C8

TIMER 1

Timer 1 Counter High-Byte Register (T1CNTH)

F6H, Set 1, R

MSB

LSB

Reset Value : 00H

Timer 1 Counter Low-Byte Register (T1CNTL)

F7H, Set 1, R

LSB

Reset Value : 00H

Timer 1 Data High-Byte Register (T1DATAH)

F8H, Set 1, R/W

LSB

Reset Value : FFh

Timer 1 Data Low-Byte Register (T1DATAL)

F9H, Set 1, R/W

LSB

Reset Value : FFh

Figure 11-4. Timer 1 Registers

11-5

TIMER 1

S3P80C5/C80C5/C80C8

NOTES

11-6

S3P80C5/C80C5/C80C8

COUNTER A

12 COUNTER A

OVERVIEW

The S3P80C5/C80C5/C80C8 microcontroller has an 8-bit counter called counter A. Counter A, which can be

used to generate the carrier frequency, has the following components (see Figure 12-1):

— Counter A control register, CACON

— 8-bit down counter with auto-reload function

— Two 8-bit reference data registers, CADATAH and CADATAL

Counter A has two functions:

— As a normal interval timer, generating a counter A interrupt (IRQ4, vector ECH) at programmed time

intervals.

— To supply a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow

interrupt.

12-1

COUNTER A

S3P80C5/C80C5/C80C8

CACON.6-.7

DIV 1

DIV 2

DIV 4

DIV 8

8-Bit

Down Counter

CACON.0

(CAOF)

CLK

To Other Block

(P3.1/REM)

MUX

CACON.3

Repeat

Control

MUX

Interrupt

Control

IRQ4

(CAINT)

INT.GEN.

Counter A Data

Low Byte Register

fOSC

CACON.2

CACON.4-.5

Counter A Data

High Byte Register

Data Bus

NOTES: The value of the CADATAL register is loaded into the 8-bit counter when the operaion of the counter A

Starts. If a borrow occurs in the counter, the value of the CADATAH register is loaded into the 8-bit

counter. However, if the next borrow ovvurs, the value of the CADATAL register is loaded into the 8-bit

counter.

Figure 12-1. Counter A Block Diagram

12-2

S3P80C5/C80C5/C80C8

COUNTER A

COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON

contains control settings for the following functions (see Figure 12-2):

— Counter A clock source selection

— Counter A interrupt enable/disable

— Counter A interrupt pending control (read for status, write to clear)

— Counter A interrupt time selection

Counter A Control Register (CACON)

F3H, Set 1, R/W

MSB

LSB

Counter A input clock

selection bits:

00 = fOSC

Counter A output flip-flop

control bit:

0 = T-FF is Low

1 = T-FF is High

01 = fOSC/2

10 = fOSC/4

11 = fOSC/8

Counter A mode selection bit:

0 = One-shot mode

1 = Repeating mode

Counter A interrupt selection bits:

00 = Elapsed time for Low data value

01 = Elapsed time for High data value

10 = Elapsed time for Low and High

data values

Counter A start/stop bit:

0 = Stop counter A

1 = Start counter A

11 = Invalid setting

Counter A interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Figure 12-2. Counter A Control Register (CACON)

12-3

COUNTER A

S3P80C5/C80C5/C80C8

Counter A Data High-Byte Register (CADATAH)

F4H, Set 1, R/W

MSB

LSB

Reset Value : FFh

Counter A Data Low-Byte Register (CADATAL)

F5H, Set 1, R/W

LSB

Reset Value : FFh

Figure 12-3. Counter A Registers

COUNTER A PULSE WIDTH CALCULATIONS

tHIGH

tLOW

To generate the above repeated waveform consisted of low period time, t_LOW, and high period time, t_HIGH

When CAOF = 0,

tLOW = (CADATAL + 2) x 1/fxx, 0H < CADATAL < 100H, where fx = The selected clock.

tHIGH = (CADATAH + 2) x 1/fxx, 0H < CADATAH < 100H, where fx = The selected clock.

When CAOF = 1,

tLOW = (CADATAH + 2) x 1/fxx, 0H < CADATAH < 100H, where fx = The selected clock.

tHIGH = (CADATAL + 2) x 1/fxx, 0H < CADATAL < 100H, where fx = The selected clock.

To make t_LOW= 24 us and t_HIGH= 15 us. f_OSC= 4 MHz, fx = 4 MHz/4 = 1 MHz

[Method 1] When CAOF = 0,

t_LOW= 24 us = (CADATAL + 2) /fx = (CADATAL + 2) ´ 1us, CADATAL = 22.

t_HIGH= 15 us = (CADATAH + 2) /fx = (CADATAH + 2) ´ 1us, CADATAH = 13.

[Method 2] When CAOF = 1,

t_HIGH= 15 us = (CADATAL + 2) /fx = (CADATAL + 2) ´ 1us, CADATAL = 13.

t_LOW= 24 us = (CADATAH + 2) /fx = (CADATAH + 2) ´ 1us, CADATAH = 22.

12-4

S3P80C5/C80C5/C80C8

COUNTER A

Counter A

Clock

CAOF = '0'

CADATAL = 01-FFH

CADATAH = 001H

High

Low

High

CAOF = '0'

CADATAL = 00H

CADATAH = 01-FFH

CAOF = '0'

CADATAL = 00H

CADATAH = 00H

CAOF = '1'

CADATAL = 00H

CADATAH = 00H

Counter A

Clock

CAOF = '0'

CADATAL = DEH

CADATAH = 1EH

20H

E0H

CAOF = '0'

CADATAL = DEH

CADATAH = 1EH

CAOF = '1'

CADATAL = 7EH

CADATAH = 7EH

80H

CAOF = '0'

CADATAL = 7EH

CADATAH = 7EH

Figure 12-4. Counter A Output flip-flop Waveforms in Repeat Mode

12-5

COUNTER A

S3P80C5/C80C5/C80C8

PROGRAMMING TIP — To Generate 38 kHz, 1/3duty Signal Through P2.1

This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source,

and CADATAH and CADATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are:

8.795 ms

17.59

37.9 kHz 1/3 Duty

— Counter A is used in repeat mode

— Oscillation frequency is 4 MHz (0.25 ms)

— CADATAH = 8.795 ms / 0.25 ms = 35.18, CADATAL = 17.59 ms / 0.25 ms = 70.36

— Set P2.1 C-MOS push-pull output and CAOF mode.

ORG

0100H

; Reset address

START

•

CADATAL,#(70-2)

CADATAH,#(35-2)

; Set 17.5 ms

; Set 8.75 ms

;

P2CON,#10101010B

CACON,#00000110B

; Set P2 to C-MOS push-pull output.

; Set P2.1 to REM output

;

; Clock Source ¬ f_OSC

; Disable Counter A interrupt.

; Select repeat mode for Counter A.

; Start Counter A operation.

; Set Counter A Output Flip-flop(CAOF) high.

;

P2,#20H

; Set P2.5(Carrier On/Off) to high.

; This command generates 38 kHz, 1/3duty pulse signal

; through P2.1

;

•

12-6

S3P80C5/C80C5/C80C8

COUNTER A

PROGRAMMING TIP — To Generate a One Pulse Signal Through P2.1

This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source,

and CADATAH and CADATAL to make a 40 ms width pulse. The program parameters are:

40 ms

— Counter A is used in one shot mode

— Oscillation frequency is 4 MHz (1 clock = 0.25 ms)

— CADATAH = 40 ms / 0.25 ms = 160, CADATAL = 1

— Set P2.1 C-MOS push-pull output and CAOF mode.

ORG

•

0100H

; Reset address

START

•

CADATAH,# (160-2)

CADATAL,# 1

; Set 40 ms

; Set any value except 00H

;

P2CON,#10101010B

CACON,#00000001B

; Set P2 to C-MOS push-pull output.

; Set P2.1 to REM output

;

; Clock Source ¬ f_OSC

; Disable Counter A interrupt.

; Select one shot mode for Counter A.

; Stop Counter A operation.

; Set Counter A Output flip-flop (CAOF) high

; Set P2.5(Carrier On/Off) to high.

P2,#20H

•

Pulse_out: LD

CACON,#00000101B

; Start Counter A operation

; to make the pulse at this point.

•

; After the instruction is executed, 0.75 ms is required

; before the falling edge of the pulse starts.

•

12-7

COUNTER A

S3P80C5/C80C5/C80C8

NOTES

12-8

S3P80C5/C80C5/C80C8

ELECTRICAL DATA

13 ELECTRICAL DATA

OVERVIEW

In this section, S3P80C5/C80C5/C80C8 electrical characteristics are presented in tables and graphs. The

information is arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in Stop mode

— Stop mode release timing when initiated by a Reset

— I/O capacitance

— A.C. electrical characteristics

— Input timing for external interrupts (port 0)

— Oscillation characteristics

— Oscillation stabilization time

13-1

ELECTRICAL DATA

S3P80C5/C80C5/C80C8

Table 13-1. Absolute Maximum Ratings

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Unit

V_DD

Supply voltage

–

– 0.3 to + 6.5

– 0.3 to V_DD+ 0.3

– 18

V_IN

V_O

Input voltage

–

All output pins

Output voltage

Output current High

I_OH

One I/O pin active

All I/O pins active

One I/O pin active

– 60

+ 30

I_OL

Output current Low

Total pin current for ports 0, 1, and 2

+ 100

+ 40

Total pin current for port 3

–

T_A

Operating

– 40 to + 85

temperature

T_STG

Storage

–

– 65 to + 150

temperature

Table 13-2. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 3.6 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DD

f_OSC4MHz

Operating Voltage

1.7

–

3.6

(Instruction clock = 0.67 MHz)

V_IH1

All input pins except V_IH2

and V_IH3

0.8 V_DD

V_DD

Input High

voltage

–

V_IH2

V_IL1

V_DD– 0.3

V_DD

All input pins except V_IL2

and V_IL3

0.2 V_DD

Input Low voltage

V_IL2

X_IN

0.3

V_OH1

V_DD= 2.4 V, I

= – 6 mA

V_DD– 0.7

Output High

voltage

Port 2.1 only, T_A= 25 C

V_OH2

V_DD= 2.4 V, I_OH= – 2.2mA V_DD0.7

–

Port 2.0, 2.2, T_A= 25 C

V_OH3

V_DD= 2.4 V, I_OH= – 1 mA

All output pins except Port2,

V_DD1.0

T_A= 25 C

13-2

S3P80C5/C80C5/C80C8

ELECTRICAL DATA

Table 13-2. D.C. Electrical Characteristics (Continued)

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 3.6 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_OL1

V_DD= 2.4 V, I_OL= 12 mA, port

Output Low

voltage

0.4

0.5

2.1 only, T_A= 25 C

V_OL2

V_OL3

I_LIH1

V_DD= 2.4 V, I_OL= 5 mA

–

0.4

–

0.5

1.0

Port 2.0,2.2, T_A= 25 C

I_OL= 1 mA

Ports 0 and 1, T_A= 25 C

V_IN= V_DD

All input pins except X_INand

X_OUT

Input High

leakage current

–

µA

I_LIH2

I_LIL1

V_IN= V_DD, X_INand X_OUT

V_IN= 0 V

Input Low

–

– 1

leakage current

All input pins except X_IN, X_OUT

I_LIL2

V_IN= 0 V

– 20

X_INand X_OUT

I_LOH

I_LOL

R_L1

V_OUT= V_DD

Output High

leakage current

–

µA

All output pins

V_OUT= 0 V

Output Low

leakage current

– 1

All output pins

V_DD= 2.4V, V_IN= 0 V;

Pull-up resistors

T_A= 25 C , Ports 0-2

I_DD1

I_DD2

Supply current

(note)

–

2.6

0.7

V_DD= 3.6 V ± 10%

4-MHz crystal

Idle mode;

2.0

V_DD= 3.6 V ± 10 %

4-MHz crystal

I_DD3

Stop mode;

V_DD= 3.6 V

–

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

13-3

ELECTRICAL DATA

S3P80C5/C80C5/C80C8

Table 13-3. Characteristics of Low Voltage Detect circuit

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Hysteresys Voltage of LVD

(Slew Rate of LVD)

–

300

V_LVD

Low level detect voltage

(S3C80C5/C80C8)

–

1.70

1.90

2.1

Table 13-4. Data Retention Supply Voltage in Stop Mode

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply

voltage

–

1.0

–

3.6

I_DDDR

V_DDDR= 1.0 V

Stop mode

Data retention supply

current

–

µA

Table 13-5. Input/output Capacitance

(T_A= – 40 C to + 85 C, V_DD= 0 V)

Parameter

Input

capacitance

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

f = 1 MHz; unmeasured pins

are connected to V_SS

—

C_OUT

C_IO

Output

capacitance

I/O capacitance

Table 13-6. A.C. Electrical Characteristics

(T_A= – 40 C to + 85 C)

Parameter

Symbol

t_INTH

t_INTL

Conditions

Min

Typ

Max

Unit

P0.0–P0.7, V_DD3.6

Interrupt input,

High, Low width

200

300

—

13-4

S3P80C5/C80C5/C80C8

ELECTRICAL DATA

tINTL

tINTH

0.8 VDD

0.2 VDD

NOTE:

The unit tCPU means one CPU clock period.

Figure 13-1. Input Timing for External Interrupts (Port 0)

Table 13-7. Oscillation Characteristics

(T_A= – 40 C + 85 C)

Oscillator Clock Circuit

Crystal

Conditions

Min

Typ

Max

Unit

CPU clock oscillation

frequency

–

MHz

XIN

XOUT

Ceramic

CPU clock oscillation

frequency

–

MHz

XT_IN

XTOUT

X_INinput frequency

External clock

External

Clock

XIN

Open Pin

OUT

13-5

ELECTRICAL DATA

S3P80C5/C80C5/C80C8

Table 13-8. Oscillation Stabilization Time

(T_A= – 40 C + 85 C, V_DD= 3.6 V)

Oscillator

Test Condition

Min

Typ

Max

Unit

f_OSC> 400 kHz

Main crystal

–

Oscillation stabilization occurs when V_DDis equal

to the minimum oscillator voltage range.

X_INinput High and Low width (t_XH, t_XL)

Main ceramic

–

External clock

(main system)

–

500

–

(1)

t_WAIT

2¹⁶/

f_OSC

Oscillator

stabilization

wait time

when released by a reset

(2)

–

t_WAIT

when released by an interrupt

NOTES:

is the oscillator frequency.

OSC

2. The duration of the oscillation stabilization time (t

in the basic timer control register, BTCON.

) when it is released by an interrupt is determined by the setting

WAIT

Instruction

Clock

Instruction

Clock

1.33 MHz

8 MHz

1.00 MHz

6 MHz

4 kHz

670 kHz

500 kHz

250 kHz

8.32 kHz

400 kHz

Supply Voltage (V)

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

A 1.7 V: 4 MHz

b 2.0 V: 8 MHz

Figure 13-2. Operating Voltage Range of S3P80C5/C80C5/C80C8

13-6

S3P80C5/C80C5/C80C8

MECHANICAL DATA

14 MECHANICAL DATA

OVERVIEW

The S3P80C5/C80C5/C80C8 microcontroller is currently available in a 24-pin SOP and SDIP package.

0-8

#24

#13

24-SOP-375

+ 0.10

0.15 - 0.05

#12

15.74 MAX

15.34 ± 0.20

0.10 MAX

1.27

(0.69)

+ 0.10

0.38 - 0.05

NOTE: Dimensions are in millimeters.

Figure 14-1. 24-Pin SOP Package Mechanical Data

14-1

MECHANICAL DATA

S3P80C5/C80C5/C80C8

#24

#13

0-15

24-SDIP-300

#12

23.35 MAX

22.95 ± 0.20

0.46 ± 0.10

0.89 ± 0.10

1.778

(1.70)

NOTE: Dimensions are in millimeters.

Figure 14-2. 24-Pin SDIP Package Mechanical Data

14-2

S3C8 SERIES MASK ROM ORDER FORM

Product description:

Device Number: S3C80C5

S3C__________- ___________(write down the ROM code number)

S3C80C8

(note)

Product Order Form:

Package

Pellet

Wafer

Package Type: __________

Package Marking (Check One):

Standard

Custom A

(Max 10 chars)

Custom B

(Max 10 chars each line)

@ YWW

Device Name

@ YWW

Device Name

SEC

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

Delivery Dates and Quantities:

Deliverable

ROM code

Required Delivery Date

Quantity

Comments

–

Not applicable

See ROM Selection Form

Customer sample

Risk order

See Risk Order Sheet

Please answer the following questions:

For what kind of product will you be using this order?

New product

Upgrade of an existing product

Other

Replacement of an existing product

If you are replacing an existing product, please indicate the former product name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Delivery on time

Development system

Used same micom before

Technical support

Quality of documentation

Samsung reputation

Mask Charge (US$ / Won):

Customer Information:

____________________________

Company Name:

___________________

________________________

(Person placing the order)

Telephone number

_________________________

Signatures:

__________________________________

(Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales

representative. Samsung sales offices are listed on the back cover of this book.)

NOTE : Please one more check whether the selected device is S3C80A4/C80A8/C80A5 or S3C80B4/C80B8/C80B5.

S3C8 SERIES

REQUEST FOR PRODUCTION AT CUSTOMER RISK

Customer Information:

Company Name:

Department:

Telephone Number:

Date:

________________________________________________________________

__________________________

Fax: _____________________________

Risk Order Information:

Device Number:

S3C80C5

S3C80C8

S3C__________- ___________(write down the ROM code number) ^(note)

Package:

Number of Pins: ____________

Package Type: _____________________

Intended Application:

Product Model Number:

________________________________________________________________

Customer Risk Order Agreement:

We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk

order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume

responsibility for any and all production risks involved.

Order Quantity and Delivery Schedule:

Risk Order Quantity:

Delivery Schedule:

_____________________ PCS

Delivery Date (s)

Quantity

Comments

Signatures:

_______________________________

(Person Placing the Risk Order)

_______________________________________

(SEC Sales Representative)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung

sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE : Please one more check whether the selected device is S3C80A4/C80A8/C80A5 or S3C80B4/C80B8/C80B5.

S3C80C5/C80C8

MASK OPTION SELECTION FORM

Device Number:

S3C80C5

S3C80C8

S3C8__________- ___________(write down the ROM code number) ^(note)

Attachment (Check one):

Diskette

PROM

Customer Checksum:

Company Name:

________________________________________________________________

Signature (Engineer):

Please answer the following questions:

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Industrials

Remocon

Caller ID

Home Appliance

Other

LCD Game

Office Automation

Please describe in detail its application

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung

sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

S3C8 SERIES OTP FACTORY WRITING ORDER FORM (1/2)

Product Description:

Device Number:

S3P80C5

S3P8__________- ___________(write down the ROM code number) ^(note)

Product Order Form:

Package

Pellet

Wafer

If the product order form is package:

Package Type: _____________________

Package Marking (Check One):

Standard

Custom A

Custom B

(Max 10 chars)

(Max 10 chars each line)

@ YWW

Device Name

SEC

Device Name

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

Delivery Dates and Quantity:

ROM Code Release Date

Required Delivery Date of Device

Quantity

Please answer the following questions:

What is the purpose of this order?

New product development

Upgrade of an existing product

Other

Replacement of an existing microcontroller

If you are replacing an existing microcontroller, please indicate the former microcontroller name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Delivery on time

Development system

Used same micom before

Technical support

Quality of documentation

Samsung reputation

Customer Information:

Company Name:

___________________

Telephone number

_________________________

Signatures:

________________________

(Person placing the order)

__________________________________

(Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung

sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

S3C80C5/C80C8

OTP FACTORY WRITING ORDER FORM (2/2)

Device Number:

S3P80C5

S3P8__________- ___________(write down the ROM code number) ^(note)

Customer Checksums:

Company Name:

_______________________________________________________________

________________________________________________________________

Signature (Engineer):

Read Protection ⁽¹⁾:

Yes

Please answer the following questions:

Are you going to continue ordering this device?

Yes No

If so, how much will you be ordering? _________________pcs

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Industrials

Remocon

Caller ID

Home Appliance

Other

LCD Game

Office Automation

Please describe in detail its application

__________________________________________________________________________

NOTES

1. Once you choose a read protection, you cannot read again the programming code from the EPROM.

2. OTP Writing will be executed in our manufacturing site.

3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors

occurred from the writing program.

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung

sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

BOOK SPINE TEXT

SAMSUNG Logo S3P80C5/C80C5/C80C8 Microcontrollers User's Manual, Rev. 1 May 2002

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