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M393T5750CZ3-CCC 参数 Datasheet PDF下载

M393T5750CZ3-CCC图片预览
型号: M393T5750CZ3-CCC
PDF下载: 下载PDF文件 查看货源
内容描述: 基于512MB DDR2 SDRAM注册模块240PIN注册模块C -死72位ECC [DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC]
分类和应用: 内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 21 页 / 476 K
品牌: SAMSUNG [ SAMSUNG ]
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512MB, 1GB, 2GB Registered DIMMs  
DDR2 SDRAM  
DDR2-800  
DDR2-667  
DDR2-533  
DDR2-400  
Symbol  
Units  
Notes  
Parameter  
min  
max  
min  
0.35  
0.35  
0.2  
max  
min  
max  
min  
max  
DQS input high pulse width  
DQS input low pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
Write postamble  
tDQSH  
tDQSL  
tDSS  
0.35  
0.35  
0.2  
0.2  
2
x
x
0.35  
0.35  
0.2  
0.2  
2
x
0.35  
0.35  
0.2  
0.2  
2
x
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ps  
x
x
x
x
x
x
x
x
tDSH  
x
0.2  
x
x
x
tMRD  
x
2
x
x
x
tWPST  
tWPRE  
tIH(base)  
tIS(base)  
tRPRE  
tRPST  
0.4  
0.35  
250  
175  
0.9  
0.4  
0.6  
x
0.4  
0.6  
x
0.4  
0.35  
375  
250  
0.9  
0.4  
0.6  
x
0.4  
0.35  
475  
350  
0.9  
0.4  
0.6  
x
Write preamble  
0.35  
275  
200  
0.9  
Address and control input hold time  
Address and control input setup time  
Read preamble  
x
x
x
x
x
x
x
x
ps  
1.1  
0.6  
1.1  
0.6  
1.1  
0.6  
1.1  
0.6  
tCK  
tCK  
Read postamble  
0.4  
Active to active command period for 1KB  
page size products  
tRRD  
7.5  
10  
35  
45  
x
x
7.5  
10  
x
x
7.5  
10  
x
x
7.5  
10  
x
x
ns  
ns  
ns  
ns  
Active to active command period for 2KB  
page size products  
tRRD  
tFAW  
Four Activate Window for 1KB page size  
products  
37.5  
50  
37.5  
50  
37.5  
50  
Four Activate Window for 2KB page size  
products  
tFAW  
CAS to CAS command delay  
Write recovery time  
tCCD  
tWR  
2
x
x
2
2
2
tCK  
ns  
15  
15  
x
x
x
15  
x
x
x
15  
x
x
x
Auto precharge write recovery + precharge  
time  
tDAL  
WR+tRP  
x
WR+tRP  
WR+tRP  
WR+tRP  
tCK  
Internal write to read command delay  
tWTR  
7.5  
7.5  
7.5  
7.5  
7.5  
7.5  
10  
7.5  
ns  
ns  
Internal read to precharge command delay tRTP  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tXSNR  
tRFC + 10  
200  
tRFC + 10  
200  
tRFC + 10  
200  
tRFC + 10  
200  
ns  
tXSRD  
x
x
x
tCK  
Exit precharge power down to any non-  
read command  
tXP  
2
2
2
2
x
x
2
2
x
x
2
2
x
x
tCK  
tCK  
tCK  
Exit active power down to read command tXARD  
Exit active power down to read command  
tXARDS  
8 - AL  
7 - AL  
6 - AL  
6 - AL  
(slow exit, lower power)  
CKE minimum pulse width  
tCKE  
tCK  
3
2
3
2
3
2
3
2
(high and low pulse width)  
ODT turn-on delay  
tAOND  
tAON  
2
2
2
2
tCK  
ns  
tAC(max)  
+ 0.7  
tAC(max)  
+0.7  
tAC(max)  
+1  
tAC(max)  
+1  
ODT turn-on  
tAC(min)  
tAC(min)  
tAC(min)  
tAC(min)  
2tCK +  
tAC(max)  
+1  
tAC(min)+  
2
tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC  
ODT turn-on(Power-Down mode)  
tAONPD  
ns  
2
(max)+1  
2
(max)+1  
2
(max)+1  
ODT turn-off delay  
ODT turn-off  
tAOFD  
tAOF  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
tCK  
ns  
tAC(max)  
+ 0.6  
tAC(max)  
+ 0.6  
tAC(max)+  
0.6  
tAC(max)+  
0.6  
tAC(min)  
tAC(min)  
tAC(min)  
tAC(min)  
2.5tCK +  
tAC(max)  
+1  
2.5tCK+  
tAC(max)  
+1  
2.5tCK+  
tAC(max)  
+1  
tAC(min)+  
2
tAC(min)+ 2.5tCK+tA tAC(min)+  
tAC(min)+  
2
ODT turn-off (Power-Down mode)  
tAOFPD  
ns  
2
C(max)+1  
2
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
3
8
0
3
8
0
3
8
0
tCK  
tCK  
ns  
12  
12  
12  
12  
Minimum time clocks remains ON after  
CKE asynchronously drops LOW  
tIS+tCK  
+tIH  
tIS+tCK  
+tIH  
tIS+tCK  
+tIH  
tIS+tCK  
+tIH  
tDelay  
ns  
Rev. 1.2 Aug. 2005  
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