512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
OPER
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
Average periodic refresh interval
tRFC
tREFI
75
105
127.5
195
327.5
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
85 °C < T
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-800(E7)
5 - 5 - 5
DDR2-667(E6)
5 - 5 - 5
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
max
min
max
min
5
max
min
max
5
8
5
8
8
5
8
ns
ns
ns
ns
ns
ns
ns
3.75
2.5
8
3.75
3
8
3.75
3.75
15
8
5
8
-
8
8
8
-
12.5
12.5
51.5
39
-
15
15
54
39
-
-
15
15
55
40
-
tRP
-
-
-
-
15
-
-
-
tRC
55
-
tRAS
70000
70000
40
70000
70000
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Symbol
Units
Notes
Parameter
min
max
400
min
-450
-400
0.45
0.45
max
min
max
+500
+450
0.55
0.55
min
-600
-500
0.45
0.45
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
- 400
- 350
0.45
0.45
+450
+400
0.55
-500
-450
0.45
0.45
+600
+500
0.55
0.55
ps
ps
tDQSCK
tCH
350
0.55
0.55
tCK
tCK
CK low-level width
tCL
0.55
min(tCL,t
CH)
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
x
x
x
ps
Clock cycle time, CL=x
tCK
2500
125
50
8000
3000
175
8000
3750
225
8000
5000
275
8000
ps
ps
ps
DQ and DM input hold time
DQ and DM input setup time
tDH(base)
tDS(base)
x
x
x
x
x
x
x
x
100
100
150
Control & Address input pulse width for
each input
tIPW
0.6
x
0.6
x
0.6
x
0.6
x
tCK
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK/CK tHZ
0.35
x
x
0.35
x
x
0.35
x
x
0.35
x
x
tCK
ps
tAC max
tAC max
tAC max
tAC max
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min tAC max tAC min tAC max
tAC min tAC max tAC min tAC max
ps
2* tAC
min
2*tAC
min
DQ low-impedance time from CK/CK
tLZ(DQ)
tAC max
tAC max 2* tACmin tAC max 2* tACmin tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
tQHS
tQH
x
200
300
x
x
240
340
x
x
x
300
400
x
x
x
350
450
x
ps
ps
ps
DQ hold skew factor
x
x
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
DQ/DQS output hold time from DQS
First DQS latching transition to associated
clock edge
tDQSS
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
Rev. 1.2 Aug. 2005
SAMSUNG [ SAMSUNG ]
