Preliminary
K5A3x80YT(B)C
MCP MEMORY
Table 8. SRAM Operation Table
1. Word Mode
CS1S
CS2S
X
OE
X
X
X
H
H
L
WE
X
BYTES
X
SA
X
X
X
X
X
X
X
X
X
X
X
LB
X
X
H
L
UB
X
X
H
X
L
D/Q0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
D/Q8~15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
H
X
X
L
L
L
L
L
L
L
L
Deselected
L
X
X
Deselected
X
X
X
Deselected
H
H
H
H
H
H
L
VccS
VccS
VccS
VccS
VccS
VccS
VccS
VccS
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
H
X
L
Active
H
H
L
Active
H
L
H
L
High-Z
Dout
Active
H
L
L
Dout
Active
H
X
X
X
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
H
L
H
L
High-Z
Din
Active
H
L
L
Din
Active
NOTE: X means don¢t care. (Must be low or high state)
2. Byte Mode
CS1S
CS2S
OE
X
WE
X
BYTES
X
SA
X
LB
X
UB
X
D/Q0~7
High-Z
High-Z
High-Z
Dout
D/Q8~15
High-Z
High-Z
DNU
Mode
Power
Standby
Standby
Active
H
X
L
L
L
X
L
Deselected
X
X
X
X
X
X
Deselected
SA1)
SA1)
SA1)
H
H
H
H
L
H
VSS
VSS
VSS
DNU
DNU
DNU
DNU
DNU
DNU
Output Disabled
Lower Byte Read
Lower Byte Write
H
DNU
Active
X
L
Din
DNU
Active
NOTE: X means don¢t care. (Must be low or high state)
DNU = Do Not Use
1) Address input for byte operation.
Revision 0.0
November 2002
- 10 -
SAMSUNG [ SAMSUNG ]
