256M GDDR3 SDRAM
K4J55323QG
4.0 PIN CONFIGURATION
Normal Package (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
VDDQ
VSSQ
VDDQ
VDD
DQ0
DQ2
VSS
DQ1
DQ3
ZQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS
MF
VSS
DQ9
VDD
DQ8
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSSQ
VDDQ
DQ11
DQ10
VSSQ WDQS0 RDQS0
VSSQ RDQS1 WDQS1
VDDQ
VDD
DQ4
DQ6
DM0
DQ5
DQ7
RAS
RFU2
A2
VDDQ
CS
DM1
DQ13
DQ15
RFM
DQ12
DQ14
VSSQ
A5
G
H
J
VSS
VSSQ
A1
BA0
BA1
WE
VSS
VREF
VSSA
VDDA
VSS
CKE
VREF
VSSA
VDDA
VSS
RFU1
A10
VDDQ
A0
VDDQ
A4
CK
A6
CK
K
L
A8/AP
VSSQ
DQ16
DQ18
VSSQ
DQ24
DQ26
DQ25
DQ27
DM3
A11
A7
DQ17
DQ19
DM2
M
N
P
R
T
VDD
A3
A9
VDD
VDDQ
VDDQ
VSSQ
VDDQ
VSSQ
SEN
VDDQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ WDQS3 RDQS3
VSSQ RDQS2 WDQS2
VDDQ
VSSQ
VDDQ
DQ28
DQ30
VDD
DQ29
DQ31
VSS
VDDQ
VSSQ
DQ21
DQ23
VSS
DQ20
DQ22
VDD
V
RESET
Note :
1. RFU1 is reserved for future use
2. RFU2 is reserved for future use
3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however,
either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3)
becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either
static HIGH or floating state on this pin will not cause any problem for the DRAM
Please refer to Mirror Function Signal Mapping table at page 6.
4 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
