256M GDDR3 SDRAM
K4J55323QG
Revision History
Revision
0.0
Month
February
March
Year
2005
2005
History
- Target Spec
0.1
- Changed EMRS table for Driver Impedance control.
- Typo corrected.
- Added clock frequency change sequence on page 18 and IBIS spec on page 19~21
- Reduced Cin min. value on page 54.
0.2
March
2005
- Added note for RFM pin on page 4.
- Modified input functional description for CK/CK and Vref on page 5.
- Removed -BC10/11 from the spec. Accordingly, CL12~15 become "reserved" in MRS table.
- Modified note description for RMF on page 4.
0.3
0.4
April
May
2005
2005
- Modified input functional description for Mirror function on page 5.
- Modified note description for the Write Latency on page 55.
- Clarify RMF description on page 4,5 to avoid confusion in case of using same board for both
512Mb and 256Mb GDDR3.
- AddednotedescriptionforBoundaryscanfunctiononpage22,23.
(one RFM ball in the scan oder will be read as a logic "0")
- Typo corrected.
1.0
1.1
June
2005
2005
- Finalized DC characteristics and IBIS specification
November
- Changed tRFC of -BC16 from 33tCK to 31tCK effective date code with WW0543
2 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
