DDR SDRAM 256Mb E-die (x4, x8)
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA package
Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
K4H560438E-GC/LB3
K4H560438E-GC/LA2
K4H560438E-GC/LB0
K4H560838E-GC/LB3
K4H560838E-GC/LA2
K4H560838E-GC/LB0
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
64M x 4
SSTL2
60 FBGA
32M x 8
SSTL2
60 FBGA
Operating Frequencies
B3(DDR333@CL=2.5)
2.5-3-3
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
2.5-3-3
CL-tRCD-tRP
Speed @CL2
Speed @CL2.5
2-3-3
133MHz
133MHz
133MHz
100MHz
166MHz
133MHz
*CL : CAS Latency
Rev. 1.3 April, 2005
SAMSUNG [ SAMSUNG ]
