DDR SDRAM 512Mb C-die (x4, x8, x16)
DDR SDRAM
19.0 AC Timming Parameters & Specifications
CC
B3
A2
B0
(DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5)
Parameter
Symbol
Unit Note
Min
55
Max
Min
60
Max
Min
65
75
45
20
Max
Min
65
75
45
20
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
Refresh row cycle time
Row active time
RAS to CAS delay
70
72
40
70K
42
70K
70K
70K
15
18
Row precharge time
15
18
20
20
Row active to Row active delay
Write recovery time
Last data in to Read command
tRRD
tWR
tWTR
10
15
2
-
6
5
12
15
1
7.5
6
15
15
1
7.5
7.5
-
15
15
1
10
7.5
-
CL=2.0
CL=2.5
CL=3.0
-
12
10
12
12
-
12
12
-
12
12
-
Clock cycle time
tCK
-
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.55
0.55
+0.6
+0.7
0.45
1.1
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
22
13
0.6
1.25
tDSH
tDQSH
tDQSL
tIS
DQS-in low level width
15, 17~19
15, 17~19
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup
tIH
ns
tIS
0.7
0.8
1.0
1.0
ns
16~19
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
tIH
tHZ
tLZ
tMRD
tDS
0.7
-0.65
-0.65
10
0.8
-0.7
-0.7
12
1.0
-0.75
-0.75
15
1.0
-0.75
-0.75
15
ns
ns
ns
ns
ns
ns
16~19
11
11
+0.65
+0.65
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
DQ & DM setup time to DQS
0.4
0.45
0.5
0.5
j, k
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
0.5
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
ns
ns
ns
tCK
us
18
18
200
200
200
200
7.8
7.8
7.8
7.8
-
14
21
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
-
20, 21
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
tQHS
tWPST
0.5
0.6
0.55
0.6
0.75
0.6
0.75
0.6
ns
tCK
21
12
0.4
15
0.4
18
0.4
20
0.4
20
tRAP
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
23
Rev. 1.1 June. 2005
SAMSUNG [ SAMSUNG ]
