K4B4G0446B
K4B4G0846B
1.0 Ordering Information
[ Table 1 ] Samsung DDP 4Gb DDR3 B-die ordering information table
Organization
1Gx4
512Mx8
DDR3-800 (6-6-6)
K4B4G0446B-MCF7
K4B4G0846B-MCF7
DDR3-1066 (7-7-7)
K4B4G0446B-MCF8
K4B4G0846B-MCF8
DDP 4Gb DDR3 SDRAM
DDR3-1333 (9-9-9)
K4B4G0446B-MCH9
K4B4G0846B-MCH9
Package
78 FBGA
78 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2.0 Key Features
[ Table 2 ] DDP 4Gb DDR3 B-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
DDQ
= 1.5V ± 0.075V
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066) and 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85°C, 3.9us at
85°C < T
CASE
< 95
°C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The DDP 4Gb DDR3 SDRAM B-die is organized as a 128Mbit x 4 I/Os x
8banks, 64Mbit x 8 I/Os x 8banks. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3-
1333) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibra-
tion, On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V
DDQ
.
The 4Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8).
Note : 1. The functionality described and the timing specifications included
in this data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device
Operation & Timing Diagram”.
Page 5 of 59
Rev. 1.0 March 2009
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
