Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
[ Table 41 ] IDD7 Measurement - Loop Pattern1)
0
1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
0
1
2
...
repeat above D Command until nRRD - 1
nRRD
nRRD + 1
nRRD + 2
...
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
repeat above D Command until 2*nRRD-1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
2
3
2 * nRRD
3 * nRRD
D
1
0
0
0
0
3
00
0
0
F
F
0
0
-
-
4
4 * nRRD
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
5
6
7
8
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
D
1
0
0
0
0
7
00
0
0
9
nFAW+4*nRRD
Assert and repeat above D Command until 2*nFAW - 1, if necessary
2*nFAW+0
2*nFAW+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
10
2*nFAW+2
Repeat above D Command until 2*nFAW + nRRD - 1
2*nFAW+nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
2*nFAW+nRRD+1
00000000
-
11
2*nFAW+nRRD+2
Repeat above D Command until 2*nFAW + 2*nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
12
13
2*nFAW+2*nRRD
2*nFAW+3*nRRD
D
1
0
0
0
0
3
00
0
0
0
0
0
0
-
-
14
2*nFAW+4*nRRD
Assert and repeat above D Command until 3*nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
15
16
17
18
3*nFAW
3*nFAW+nRRD
3*nFAW+2*nRRD
3*nFAW+3*nRRD
D
1
0
0
0
0
7
00
0
0
19
3*nFAW+4*nRRD
Assert and repeat above D Command until 4*nFAW - 1, if necessary
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.
- 40 -
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