Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in Table 18 and Figure 6.
[ Table 18 ] Single-ended output slew rate definition
Measured
Description
Defined by
From
To
VOH(AC)-VOL(AC)
Delta TRse
VOL(AC)
VOH(AC)
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
VOH(AC)-VOL(AC)
Delta TFse
VOH(AC)
VOL(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 19 ] Single-ended output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
Max
Min
1.75
2.5
Max
51)
Min
1.75
2.5
Max
51)
Min
1.75
2.5
Max
51)
51)
1.35V
1.5V
1.75
2.5
V/ns
V/ns
Single ended output slew rate
Description : SR : Slew Rate
SRQse
5
5
5
5
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in
the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining
DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
V
OH(AC)
V
V
TT
OL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
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