KM62256C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falingl time : 5ns
input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
CMOS SRAM
C
L
1)
1. Including scope and jig capacitance
A
C CHARACTERISTICS
(Vcc=4.5~5.5V, KM62256C Family : T
A
=0 to 70°C, KM62256CE Family : T
A
=-25 to 85°C,
KM62256CI Family : T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
5
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
5
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
30
30
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
V
DR
KM62256CL
KM62256CL-L
Data retention current
I
DR
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
Data retention set-up time
Recovery time
t
SDR
t
RDR
Vcc=3.0V
CS≥Vcc-0.2V
Symbol
Test Condition
CS≥Vcc-0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
L-Ver
LL-Ver
See data retention waveform
Min
2.0
-
-
-
-
-
-
0
5
Typ
-
1
0.5
-
-
-
-
-
-
Max
5.5
50
10
50
25
50
25
-
-
ms
µA
Unit
V
5
Revision 4.0
December 1997
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
