STU/D413S
S a mHop Microelectronics C orp.
Ver 1.0
P-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V
DSS
-40V
FEATURES
Super high dense cell design for low R
DS(ON)
.
Rugged and reliable.
Suface Mount Package.
ESD Protected.
I
D
-19A
R
DS(ON)
(m
Ω
) Max
48
@
VGS=10V
78
@
VGS=4.5V
G
S
G
D
S
STU SERIES
TO - 252AA( D - PAK )
STD SERIES
TO - 251 ( I - PAK )
ABSOLUTE MAXIMUM RATINGS (
T
A
=25
°
C unless otherwise noted
)
Symbol
Parameter
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J,
T
STG
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
a
Limit
-40
±20
-19
-15
-58
16
Units
V
V
A
A
A
mJ
W
W
°C
T
C
=25°C
T
C
=70°C
d
-Pulsed
b
Sigle Pulse Avalanche Energy
Maximum Power Dissipation
a
T
C
=25°C
T
C
=70°C
32
20
-55 to 150
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R
JC
Thermal Resistance, Junction-to-Case
a
R
JA
Thermal Resistance, Junction-to-Ambient
4
a
°C/W
°C/W
50
Details are subject to change without notice.
Aug,08,2008
1
www.samhop.com.tw
SAMHOP [ SAMHOP MICROELECTRONICS CORP. ]
