STU/D320S
S a mHop Microelectronics C orp.
Ver 1.0
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V
DSS
30V
FEATURES
Super high dense cell design for low R
DS(ON)
.
Rugged and reliable.
TO-252 and TO-251 Package.
I
D
30A
R
DS(ON)
(m
Ω
) Max
20
@
VGS=10V
29
@
VGS=4.5V
ESD Protected.
D
D
G
S
G
D
G
S
STU SERIES
TO-252AA(D-PAK)
STD SERIES
TO-251(l-PAK)
S
ABSOLUTE
Symbol
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J,
T
STG
MAXIMUM RATINGS (
T
C
=25
°
C unless otherwise noted
)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Avalanche Energy
d
Maximum Power Dissipation
a
b
a
Limit
30
±20
30
24
120
15
e
Units
V
V
A
A
A
mJ
W
W
°C
T
C=
25 °C
T
C=
70 °C
T
C=
25 °C
T
C=
70 °C
32
20
-55 to 150
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R
JC
R
JA
Thermal Resistance, Junction-to-Case
a
Thermal Resistance, Junction-to-Ambient
a
4
50
°C/W
°C/W
Aug,11,2008
1
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