S T U/D420S
S amHop Microelectronics C orp.
J uly 05
,
2006
N-C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V
DS S
40V
F E AT UR E S
( m
W
)
I
D
24A
R
DS (ON)
Max
S uper high dense cell design for low R
DS (ON
).
24 @ V
G S
= 10V
30 @ V
G S
= 4.5V
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
D
G
S
G
D
S
G
S TU S E R IE S
TO-252AA(D-P AK)
S TD S E R IE S
TO-251(l-P AK)
S
ABS OLUTE MAXIMUM R ATINGS (T
A
=25 C unless otherwise noted)
P arameter
Drain-S ource Voltage
Gate-S ource Voltage
Drain C urrent-C ontinuous
b
-P ulsed
a
S ymbol
V
DS
V
GS
@ T
C
=25 C
I
D
I
DM
I
S
P
D
T
J
, T
S TG
Limit
40
20
24
75
8
50
-55 to 175
Unit
V
V
A
A
A
W
C
Drain-S ource Diode Forward C urrent
Maximum P ower Dissipation @ Tc=25 C
Operating and S torage Temperature R ange
THE R MAL C HAR AC TE R IS TIC S
Thermal R esistance, Junction-to-C ase
Thermal R esistance, Junction-to-Ambient
R
JC
R
JA
3
50
C /W
C /W
1
SAMHOP [ SAMHOP MICROELECTRONICS CORP. ]
