S T U/D426S
S amHop Microelectronics C orp.
Oct,2007 ver1.1
N-C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V
DS S
40V
F E AT UR E S
S uper high dense cell design for low R
DS (ON
).
I
D
53A
R
DS (ON) ( m
Ω
)
T yp
8 @ V
G S
= 10V
10 @ V
G S
= 4.5V
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
D
G
S
G
D
S
G
S TU S E R IE S
TO-252AA(D-P AK)
S TD S E R IE S
TO-251(l-P AK)
S
ABS OLUTE MAXIMUM R ATINGS (Ta=25 C unless otherwise noted)
Parameter
Drain-S ource Voltage
Gate-S ource Voltage
Drain Current-Continuous
a
S ymbol
V
DS
V
GS
@ Ta= 25 C
I
D
I
DM
I
S
I
AS
E
AS
@
Ta= 25 C
P
D
T
J
, T
S TG
Limit
40
20
53
100
20
Unit
V
V
A
A
A
A
mJ
W
C
-Pulsed
Drain-S ource Diode Forward Current
Avalanche Current
Avalanche Energy
c
c
20
100
50
-55 to 175
Maximum P ower Dissipation
Operating Junction and S torage
Temperature R ange
THE R MAL C HAR AC TE R IS TIC S
Thermal R esistance, Junction-to-C ase
Thermal R esistance, Junction-to-Ambient
R
JC
R
JA
3
50
C /W
C /W
1
SAMHOP [ SAMHOP MICROELECTRONICS CORP. ]
