三合微科股�½有限公司
S
AM
H
OP
Microelectronics Corp.
SM5032C/D
DECODER
FUNCTION DESCRIPTION
A. Decoder Signal Input Format
Bit Format
455KHz/ 192
Logic 1 is
Logic 0 is
EMPTY
Frame Format
There are four frames, each frame contains four fields while receiving:
a) Frame Head / Three-Bits
1 1 0 (Metal Option )
b) Custom Code / Two-Bits
C1
C2
c) Control Word / Seven-Bits
0000001~1000110
d) Synch Filed / Four-Bits of Empty
B. Receiver Code Table
Start Word
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Custom Code B1
C1
C1
C1
C1
C1
C1
C1
C1
C2
C2
C2
C2
C2
C2
C2
C2
0
0
0
0
0
0
1
1
B2
0
0
0
0
0
1
0
0
B3
0
0
0
0
1
0
0
0
B4
0
0
0
1
0
0
0
0
B5
0
0
1
0
0
0
0
1
B6
0
1
0
0
0
0
1
1
B7
1
0
0
0
0
0
1
0
Receiver
CP1
CP2
CP3
CP4
CP5
CP6
CP7/TP2
CP8/TP1
Page 3
V.1.0 May 28,2002