SA9904B
Voltage Sense Inputs (IVP1, IVP2, IVP3)
OUTPUT SIGNALS
Figure 8 shows the voltage sense input configuration for one
channel. The circuit is identical for the other two channels.
The voltage sense input saturates at an input current of
±17.6μARMS (±25μAPEAK). The current into the voltage sense
input should therefore be set to 14μARMS at nominal mains
voltage (VNOM) to allow for a mains voltage variation of up to
+15% and –50% without saturating the voltage sense input.
Serial Data Out (DO)
The DO pin is the serial data output pin for the SA9904B. The
Serial Clock (SCK) determines the data output rate. Data is
only transferred out on the rising edge of SCK during active
chip select (CS). This output is tri-state when CS is inactive
(low). It is recommended to use an external pull-up or pull-
down resistor on DO to ensure its state is always valid.
For best performance the SA9904B also requires an anti-
alias filter on the voltage sense inputs. Referring to Figure 8,
the capacitor C1 is used to both implement the anti-alias filter
as well as compensating for any phase shift caused by the
current transformer. The resistor R4 defines the input current
into the device. The optimum input network is achieved by
setting R4 in the order of 100k. If R4 is made too large the
capacitor C1 will be very small and the accuracy of the phase
compensation could be affected by stray capacitances.
Mains Voltage Zero Crossover (F50)
The F50 output generates a signal, which follows the mains
voltage zero crossings as shown in Figure 9. This output
generates a pulse on the rising edge of the mains voltage
zero crossing point. The pulse width is between 1ms and
2ms. Internal logic ensures that this signal is generated from
a valid phase. Should all three phases be missing but power
still applied to the SA9904B this output will generate a
constant 54Hz signal. The microcontroller can use this signal
to extract the mains timing or synchronize to the mains
voltage.
R1
R2
R3
R4
VNOM
Voltage In
Neutral
IVP
14µARMS
GND
R5 << R4 << (R1 + R2 + R3)
C1
R5
Phase
Voltage
t
GND
GND
Figure 8: Voltage sense input configuration
F50
Serial Clock (SCK)
The SCK pin is used to synchronize data interchange
between the microcontroller and the SA9904B. The clock
signal on this pin is generated by the microcontroller and
determines the data transfer rate of the DO and DI pins.
1ms – 2ms
Figure 9: Mains voltage zero crossover
SPI INTERFACE
Serial Data In (DI)
Description
The DI pin is the serial data input pin for the SA9904B. Data
will be input at a rate determined by the Serial Clock (SCK).
Data will be strobed by the SA9904B on the rising edge of
SCK only during an active chip select (CS).
A serial peripheral interface bus (SPI) is a synchronous bus
used for data transfers between a microcontroller and the
SA9904B. The pins DO (Serial Data Out), DI (Serial Data In),
CS (Chip Select), and SCK (Serial Clock) are used in the bus
implementation. The SA9904B is the slave device with the
microcontroller being the bus master. The CS input initiates
and terminates data transfers. A SCK signal (generated by
the microcontroller) strobes data between the microcontroller
and the SA9904B. The DI and DO pins are the serial data
input and output pins for the SA9904B respectively.
Chip Select (CS)
The CS input is used to address the SA9904B. A high level
on this pin enables the SA9904B to initiate data exchange.
SPEC-0447 (REV. 7)
29-09-2017
10/18
SAMES [ SAMES ]
