SA9903B
Register Access
microcontroller requires an 8 bit SPI word length. The
following sequence is valid:
0 0 0 0 0 0 0 1 1 0 A5 A4 A3 A2 A1 A0
Table 1 lists the various register addresses. The SA9903B
contains four 24 bit registers representing the active energy,
reactive energy the mains voltage and the mains frequency.
Registers may be read individually and in any order. After a
register has been read, the contents of the next register will
be shifted out on the DO pin with every SCK clock cycle. This
allows multiple subsequent registers to be read. Data output
on DO will continue until CS is inactive. The DO pin is tri-state
when CS is inactive, allowing multiple SPI devices to be
connected to the bus. The content of each register consists
of 24 bits of data. The most significant bit is shifted out first.
Table 1: Register Addressing
Address Bits
Header
Bits
ID Register
5 4 3 2 1 0
1
2
3
4
Active energy
1 1 0 X X 0 0 0 0
1 1 0 X X 0 0 0 1
1 1 0 X X 0 0 1 0
1 1 0 X X 1 0 1 1
Reactive energy
Voltage
Frequency
Data Format
Figure 11 shows the SPI waveforms and Figure 10 and Table
2 the timing information. After the least significant digit of the
address has been entered on the rising edge of SCK, the
output DO goes low. Each subsequent rising edge transition
on the SCK pin will validate the next data bit on the DO pin.
For best reliability of the SPI interface it is recommended to
change CS and DI together with the falling edge of SCK and
strobe DO on the falling edge of SCK as well, as shown in
Figure 11.
The header bits 110 (0x06) form the read command and must
precede the 6 bit address of the register being accessed.
When CS is high, data on the DI pin is clocked into the
SA9903B on the rising edge of SCK. Figure 11 shows the
data clocked into DI comprising of:
1 1 0 A5 A4 A3 A2 A1 A0
Address locations A5 and A4 are included for compatibility
with future developments. Their state is ignored at present
but it is best to set them to zero. The 9 bits needed for register
addressing can be padded with leading zeros when the
Table 2: SPI timing information
Parameter Description
Min
Max
t1
t2
SCK rising edge to DO valid 625ns 1.16µs
CS
Setup time for DI and CS
20ns
t2
t3
t4
before rising edge of SCK
SCK
DI
t3
t4
SCK minimum high time
SCK minimum low time
625ns
625ns
t5
Hold time for DI and CS
after rising edge of SCK
t5
625ns
t1
DO
Figure 10: SPI waveform timing diagram
CS
SCK
DI
Read Command
Register Address
A4
A2
A0
1
1
0
A5
A3
A1
Next Register
Register Data
D23 D22
High Impedance
0
D21
D1
D0
D23
D22
D1
D0
DO
Figure 11: SPI Waveforms
SPEC-0051 (REV. 5)
29-09-2017
11/17
SAMES [ SAMES ]
