SA9604A
SPI TIMING
Parameter Description
Min
Max Unit
t1
t2
SCK rising edge for data valid
1,160 µS
Setup time for DI and CS before the rising edge
of SCK
0,560
0,625
0,625
µS
µS
µS
t3
t4
SCK min high time
SCK min low time
5.6 Synchronised Reading of Registers
The SA9604A integrated circuit updates the registers on a continual basis. The
SA9604A register content in latched onto the SPI interface as soon as a read
command has been detected or the next register is addressed during continual
access. The registers can be accessed at any time however for maximum stability
thetimebetweenreadingsmustbeinmultiplesof8mainscycles. Theinternaloffset
cancellation procedure requires 8 mains cycles to complete. The registers are not
reset after access, so in order to determine the correct register value the previous
value read must be subtracted from the current reading. This methodology holds
true for Active, Reactive and Voltage registers. The data read from the registers
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sa m e s
SAMES [ SAMES ]
