SA9603B
ssaammeess
(25Hz square wave for 50Hz mains system). Bit D18 displays a
frequency of D17/2 and D19 displays a frequency of D17/4.
subsequent registers will be output on the DO pin. Transfer will
continue until CS is brough inactive.
Bits D16, D20, D21, D22 and D23 are not used.
To enable registers for reading, the sequence 1 1 0 (6 ) must
HEX
precede the 6 bit address of the register being accessed.
SPI Waveforms
The waveforms to perform a read cycle are shown in Figure 4:
The various register addresses are shown in the table below:
ID REGISTER A5 A4 A3 A2 A1 A0
1 Active
SPI Timing
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
2
Reactive
Voltage
3
SCK
t3
t4
4
Frequency
Address locations A5 and A4 are included for compatibility with
future developments. When CS is HIGH, data input on pin DI is
clocked into the device on the rising edge of SCK. The data
clocked into DI will comprise of 1 1 0 A5 A4 A3 A2 A1 A0, in this
order.
DI
t2
t5
DO
t1
Data Output
After the least significant digit of the address has been entered
on the rising edge of SCK, the output DO goes low with falling
edge of SCK. Each subsequent falling edge transaction on the
SCK pin will validate data of the register contents on pin DO.
CS
DR-01545
Parameter Description
Min
Max
The contents of each register consists of 24 bits of data output
on pin D0, starting with the most significant digit, D23.
t1
t3
t2
t2
SCK rising edge to DO valid 625µs 1.160µs
SCK min high time
625µs
625µs
20µs
Frequency Register
For the frequency register only bits D15 … D0 are used for
calculations. The upper seven bits (D23 … D17) must still be
clocked out, as important frequency information can be
derived from these data bits.
SCK min low time
Setup time for DI and CS
before the rising edge of SCK
t5
625µs
DI hold time
Bit D17 changes with every rising edge of the mains voltage
CS
Next register clocked out
SCK
Register ID# Address
A3
Read command
A5
A4
A2
A0
A1
1
1
0
D1
Register ID# Data
D0
Register ID# + 1 Data
D23 D22 D1
D0
D23 D22
D0
DR-01544
Figure 4: SPI Waveforms
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