SA9203/5
PIN DESCRIPTION for SA9203
Pin
Type Designation
18,52
VDD
1,35
VSS
61..68 I/O AD0..AD7
Description
+5V Supply Input
0V ground Reference
3-state address/data lines that interface with the CPU
lower 8-bit address/data bus. The 8-bit address is
latched into the SA9203 internal address latch on the
falling edge of ALE. The 8-bit data is respectively
written into and read out of the SA9203 on WR and RD
signals.
Not connected.
Active low input signal used to select the device.
This control signal latches the address on the AD0..7
lines on the falling edge of ALE.
Input low on this line enables the data bus buffers.
Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.
If enabled via A.6, this output will be set (active edge
polarity programmed by D6 and output polarity
programmed via D7 of the Port B-F direction control
register) after data has been latched into PORT A.
Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).
Input data on PORT A pins will be latched when STB is
active and transparent otherwise (polarity programmed
by D5 of the Port B-F direction control register)
8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin. In addition,each pin of PORT
A selected as an input can be programmed to be
latched or transparent.
8 general purpose I/O pins comprising PORT B. All 8
pins are programmed to be either latched outputs or
transparent inputs.
Identical to PORT B
Identical to PORT B
Identical to PORT B
Identical to PORT B
5/14
2
3
4
5
6
I
I
I
I
N/C
CS
ALE
RD
WR
7
O
INT
8
I
RST
9
I
STB
10..17
I/O
PA0..PA7
19..26
I/O
PB0..PB7
27..34
36..43
44..51
53..60
I/O
I/O
I/O
I/O
PC0..PC7
PD0..PD7
PE0..PE7
PF0..PF7
sames
SAMES [ SAMES ]
